<div dir="ltr"><br><div class="gmail_extra"><br><br><div class="gmail_quote">On Wed, Oct 16, 2013 at 1:23 AM, <span dir="ltr"><<a href="mailto:praveen@multicorewareinc.com" target="_blank">praveen@multicorewareinc.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"># HG changeset patch<br>
# User Praveen Tiwari<br>
# Date 1381904622 -19800<br>
# Node ID 0c17033defe6a1c8a0ea106c62171fc99a886f9c<br>
# Parent 203a9b334293c50a3e8741352726f2eef71dddb3<br>
fixed PIC issue with 64-bit build<br></blockquote><div><br></div><div>I'm assuming this patch was superceded by the other patches</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<br>
diff -r 203a9b334293 -r 0c17033defe6 source/common/x86/asm-primitives.cpp<br>
--- a/source/common/x86/asm-primitives.cpp Tue Oct 15 22:30:30 2013 +0530<br>
+++ b/source/common/x86/asm-primitives.cpp Wed Oct 16 11:53:42 2013 +0530<br>
@@ -280,7 +280,7 @@<br>
p.sa8d[BLOCK_8x8] = x265_pixel_sa8d_8x8_sse4;<br>
p.sa8d[BLOCK_16x16] = x265_pixel_sa8d_16x16_sse4;<br>
SA8D_INTER_FROM_BLOCK(sse4);<br>
-#if !defined(X86_64) // will go away tommorow once PIC issue is fixed for 64-bit build<br>
+<br>
p.chroma_hpp[CHROMA_PARTITION_W2] = x265_interp_4tap_horiz_pp_w2_sse4;<br>
p.chroma_hpp[CHROMA_PARTITION_W4] = x265_interp_4tap_horiz_pp_w4_sse4;<br>
p.chroma_hpp[CHROMA_PARTITION_W6] = x265_interp_4tap_horiz_pp_w6_sse4;<br>
@@ -288,7 +288,6 @@<br>
p.chroma_hpp[CHROMA_PARTITION_W12] = x265_interp_4tap_horiz_pp_w12_sse4;<br>
p.chroma_hpp[CHROMA_PARTITION_W16] = x265_interp_4tap_horiz_pp_w16_sse4;<br>
p.chroma_hpp[CHROMA_PARTITION_W32] = x265_interp_4tap_horiz_pp_w32_sse4;<br>
-#endif<br>
}<br>
if (cpuMask & X265_CPU_AVX)<br>
{<br>
diff -r 203a9b334293 -r 0c17033defe6 source/common/x86/ipfilter8.asm<br>
--- a/source/common/x86/ipfilter8.asm Tue Oct 15 22:30:30 2013 +0530<br>
+++ b/source/common/x86/ipfilter8.asm Wed Oct 16 11:53:42 2013 +0530<br>
@@ -165,7 +165,7 @@<br>
;-----------------------------------------------------------------------------<br>
%macro IPFILTER_CHROMA 1<br>
INIT_XMM sse4<br>
-cglobal interp_4tap_horiz_pp_w%1, 6, 7, 6, src, srcstride, dst, dststride, height, coeffIdx<br>
+cglobal interp_4tap_horiz_pp_w%1, 5, 7, 6, src, srcstride, dst, dststride, height<br>
%define coef2 m5<br>
%define Tm0 m4<br>
%define Tm1 m3<br>
@@ -173,7 +173,14 @@<br>
%define x1 m1<br>
%define x0 m0<br>
<br>
-movd coef2, [tab_coeff + r5d * 4]<br>
+mov r5d, r5m<br>
+<br>
+%ifdef PIC<br>
+lea r6, [tab_coeff]<br>
+movd coef2, [r6 + r5 * 4]<br>
+%else<br>
+movd coef2, [tab_coeff + r5 * 4]<br>
+%endif<br>
<br>
pshufd coef2, coef2, 0<br>
mova x2, [tab_c_512]<br>
@@ -202,7 +209,7 @@<br>
;-----------------------------------------------------------------------------<br>
%macro IPFILTER_CHROMA_W 1<br>
INIT_XMM sse4<br>
-cglobal interp_4tap_horiz_pp_w%1, 6, 7, 7, src, srcstride, dst, dststride, height, coeffIdx<br>
+cglobal interp_4tap_horiz_pp_w%1, 5, 7, 7, src, srcstride, dst, dststride, height<br>
%define coef2 m6<br>
%define Tm0 m5<br>
%define Tm1 m4<br>
@@ -211,7 +218,14 @@<br>
%define x1 m1<br>
%define x0 m0<br>
<br>
-movd coef2, [tab_coeff + r5d * 4]<br>
+mov r5d, r5m<br>
+<br>
+%ifdef PIC<br>
+lea r6, [tab_coeff]<br>
+movd coef2, [r6 + r5 * 4]<br>
+%else<br>
+movd coef2, [tab_coeff + r5 * 4]<br>
+%endif<br>
<br>
pshufd coef2, coef2, 0<br>
mova x2, [tab_c_512]<br>
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</blockquote></div><br><br clear="all"><div><br></div>-- <br>Steve Borho
</div></div>