<div dir="ltr"><br><div class="gmail_extra"><br><br><div class="gmail_quote">On Mon, Oct 28, 2013 at 7:19 AM, <span dir="ltr"><<a href="mailto:dnyaneshwar@multicorewareinc.com" target="_blank">dnyaneshwar@multicorewareinc.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"># HG changeset patch<br>
# User Dnyaneshwar Gorade <<a href="mailto:dnyaneshwar@multicorewareinc.com">dnyaneshwar@multicorewareinc.com</a>><br>
# Date 1382962711 -19800<br>
# Mon Oct 28 17:48:31 2013 +0530<br>
# Node ID fbf591d02665dcbe3d3029cc68d94ca34fd8dbab<br>
# Parent a44e10ccd754dcd8a5c24bc078c1912fa80782a0<br>
asm: assembly code for pixel_sad_16x12<br></blockquote><div><br></div><div>queued for default,</div><div><br></div><div>If you can get ASM coverage for 4x16 and 8x32, we can remove a number of intrinsic functions</div><div>
</div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
diff -r a44e10ccd754 -r fbf591d02665 source/common/x86/asm-primitives.cpp<br>
--- a/source/common/x86/asm-primitives.cpp Mon Oct 28 16:16:08 2013 +0530<br>
+++ b/source/common/x86/asm-primitives.cpp Mon Oct 28 17:48:31 2013 +0530<br>
@@ -237,6 +237,8 @@<br>
<br>
p.sad[LUMA_16x32] = x265_pixel_sad_16x32_sse2;<br>
p.sad[LUMA_16x64] = x265_pixel_sad_16x64_sse2;<br>
+ p.sad[LUMA_16x12] = x265_pixel_sad_16x12_sse2;<br>
+<br>
<br>
ASSGN_SSE(sse2);<br>
INIT2(sad, _sse2);<br>
diff -r a44e10ccd754 -r fbf591d02665 source/common/x86/sad-a.asm<br>
--- a/source/common/x86/sad-a.asm Mon Oct 28 16:16:08 2013 +0530<br>
+++ b/source/common/x86/sad-a.asm Mon Oct 28 17:48:31 2013 +0530<br>
@@ -295,6 +295,21 @@<br>
movd eax, m0<br>
RET<br>
<br>
+;-----------------------------------------------------------------------------<br>
+; int pixel_sad_16x12( uint8_t *, intptr_t, uint8_t *, intptr_t )<br>
+;-----------------------------------------------------------------------------<br>
+cglobal pixel_sad_16x12, 4,4,3<br>
+ pxor m0, m0<br>
+<br>
+ PROCESS_SAD_4x16<br></blockquote><div><br></div><div>this is roughly the same perf as the intrinsic function, but it seems like it could be done more efficiently. But since this is a rarely used block size it has lower priority than getting general coverage for 8,16, 32, and 64</div>
<div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
+ PROCESS_SAD_4x16<br>
+ PROCESS_SAD_4x16<br>
+<br>
+ movhlps m1, m0<br>
+ paddd m0, m1<br>
+ movd eax, m0<br>
+ RET<br>
+<br>
%endmacro<br>
<br>
INIT_XMM sse2<br>
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</blockquote></div><br><br clear="all"><div><br></div>-- <br>Steve Borho
</div></div>