<div dir="ltr"><br><div class="gmail_extra"><br><br><div class="gmail_quote">On Thu, Nov 7, 2013 at 6:01 AM, <span dir="ltr"><<a href="mailto:yuvaraj@multicorewareinc.com" target="_blank">yuvaraj@multicorewareinc.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"># HG changeset patch<br>
# User Yuvaraj Venkatesh <<a href="mailto:yuvaraj@multicorewareinc.com">yuvaraj@multicorewareinc.com</a>><br>
# Date 1383825592 -19800<br>
# Thu Nov 07 17:29:52 2013 +0530<br>
# Node ID d956fd7741f2314a12bbbf529796589d4d6388bf<br>
# Parent 519267d0fce9bf4b2f5ec52fe6ddc08a274f16bd<br>
asm: assembly code for pixel_sad_x4_64xN<br></blockquote><div><br></div><div><br></div><div>Nice; now the last SAD intrinsic functions can be removed; pixel-sse41.cpp just reduced in size by 2/3.</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<br>
diff -r 519267d0fce9 -r d956fd7741f2 source/common/x86/asm-primitives.cpp<br>
--- a/source/common/x86/asm-primitives.cpp Thu Nov 07 16:40:20 2013 +0530<br>
+++ b/source/common/x86/asm-primitives.cpp Thu Nov 07 17:29:52 2013 +0530<br>
@@ -420,6 +420,10 @@<br>
p.sad_x3[LUMA_64x32] = x265_pixel_sad_x3_64x32_ssse3;<br>
p.sad_x3[LUMA_64x48] = x265_pixel_sad_x3_64x48_ssse3;<br>
p.sad_x3[LUMA_64x64] = x265_pixel_sad_x3_64x64_ssse3;<br>
+ p.sad_x4[LUMA_64x16] = x265_pixel_sad_x4_64x16_ssse3;<br>
+ p.sad_x4[LUMA_64x32] = x265_pixel_sad_x4_64x32_ssse3;<br>
+ p.sad_x4[LUMA_64x48] = x265_pixel_sad_x4_64x48_ssse3;<br>
+ p.sad_x4[LUMA_64x64] = x265_pixel_sad_x4_64x64_ssse3;<br>
<br>
p.luma_hvpp[LUMA_8x8] = x265_interp_8tap_hv_pp_8x8_ssse3;<br>
p.ipfilter_sp[FILTER_V_S_P_8] = x265_interp_8tap_v_sp_ssse3;<br>
@@ -480,6 +484,10 @@<br>
p.sad_x3[LUMA_64x32] = x265_pixel_sad_x3_64x32_avx;<br>
p.sad_x3[LUMA_64x48] = x265_pixel_sad_x3_64x48_avx;<br>
p.sad_x3[LUMA_64x64] = x265_pixel_sad_x3_64x64_avx;<br>
+ p.sad_x4[LUMA_64x16] = x265_pixel_sad_x4_64x16_avx;<br>
+ p.sad_x4[LUMA_64x32] = x265_pixel_sad_x4_64x32_avx;<br>
+ p.sad_x4[LUMA_64x48] = x265_pixel_sad_x4_64x48_avx;<br>
+ p.sad_x4[LUMA_64x64] = x265_pixel_sad_x4_64x64_avx;<br>
}<br>
if (cpuMask & X265_CPU_XOP)<br>
{<br>
diff -r 519267d0fce9 -r d956fd7741f2 source/common/x86/sad-a.asm<br>
--- a/source/common/x86/sad-a.asm Thu Nov 07 16:40:20 2013 +0530<br>
+++ b/source/common/x86/sad-a.asm Thu Nov 07 17:29:52 2013 +0530<br>
@@ -2710,6 +2710,230 @@<br>
lea r3, [r3 + r4 * 2]<br>
%endmacro<br>
<br>
+%macro SAD_X4_64x4 0<br>
+ mova m4, [r0]<br>
+ mova m5, [r0 + 16]<br>
+ movu m6, [r1]<br>
+ psadbw m6, m4<br>
+ paddd m0, m6<br>
+ movu m6, [r1 + 16]<br>
+ psadbw m6, m5<br>
+ paddd m0, m6<br>
+ movu m6, [r2]<br>
+ psadbw m6, m4<br>
+ paddd m1, m6<br>
+ movu m6, [r2 + 16]<br>
+ psadbw m6, m5<br>
+ paddd m1, m6<br>
+ movu m6, [r3]<br>
+ psadbw m6, m4<br>
+ paddd m2, m6<br>
+ movu m6, [r3 + 16]<br>
+ psadbw m6, m5<br>
+ paddd m2, m6<br>
+ movu m6, [r4]<br>
+ psadbw m6, m4<br>
+ paddd m3, m6<br>
+ movu m6, [r4 + 16]<br>
+ psadbw m6, m5<br>
+ paddd m3, m6<br>
+ mova m4, [r0 + 32]<br>
+ mova m5, [r0 + 48]<br>
+ movu m6, [r1 + 32]<br>
+ psadbw m6, m4<br>
+ paddd m0, m6<br>
+ movu m6, [r1 + 48]<br>
+ psadbw m6, m5<br>
+ paddd m0, m6<br>
+ movu m6, [r2 + 32]<br>
+ psadbw m6, m4<br>
+ paddd m1, m6<br>
+ movu m6, [r2 + 48]<br>
+ psadbw m6, m5<br>
+ paddd m1, m6<br>
+ movu m6, [r3 + 32]<br>
+ psadbw m6, m4<br>
+ paddd m2, m6<br>
+ movu m6, [r3 + 48]<br>
+ psadbw m6, m5<br>
+ paddd m2, m6<br>
+ movu m6, [r4 + 32]<br>
+ psadbw m6, m4<br>
+ paddd m3, m6<br>
+ movu m6, [r4 + 48]<br>
+ psadbw m6, m5<br>
+ paddd m3, m6<br>
+<br>
+ mova m4, [r0 + FENC_STRIDE]<br>
+ mova m5, [r0 + 16 + FENC_STRIDE]<br>
+ movu m6, [r1 + r5]<br>
+ psadbw m6, m4<br>
+ paddd m0, m6<br>
+ movu m6, [r1 + 16 + r5]<br>
+ psadbw m6, m5<br>
+ paddd m0, m6<br>
+ movu m6, [r2 + r5]<br>
+ psadbw m6, m4<br>
+ paddd m1, m6<br>
+ movu m6, [r2 + 16 + r5]<br>
+ psadbw m6, m5<br>
+ paddd m1, m6<br>
+ movu m6, [r3 + r5]<br>
+ psadbw m6, m4<br>
+ paddd m2, m6<br>
+ movu m6, [r3 + 16 + r5]<br>
+ psadbw m6, m5<br>
+ paddd m2, m6<br>
+ movu m6, [r4 + r5]<br>
+ psadbw m6, m4<br>
+ paddd m3, m6<br>
+ movu m6, [r4 + 16 + r5]<br>
+ psadbw m6, m5<br>
+ paddd m3, m6<br>
+ mova m4, [r0 + 32 + FENC_STRIDE]<br>
+ mova m5, [r0 + 48 + FENC_STRIDE]<br>
+ movu m6, [r1 + 32 + r5]<br>
+ psadbw m6, m4<br>
+ paddd m0, m6<br>
+ movu m6, [r1 + 48 + r5]<br>
+ psadbw m6, m5<br>
+ paddd m0, m6<br>
+ movu m6, [r2 + 32 + r5]<br>
+ psadbw m6, m4<br>
+ paddd m1, m6<br>
+ movu m6, [r2 + 48 + r5]<br>
+ psadbw m6, m5<br>
+ paddd m1, m6<br>
+ movu m6, [r3 + 32 + r5]<br>
+ psadbw m6, m4<br>
+ paddd m2, m6<br>
+ movu m6, [r3 + 48 + r5]<br>
+ psadbw m6, m5<br>
+ paddd m2, m6<br>
+ movu m6, [r4 + 32 + r5]<br>
+ psadbw m6, m4<br>
+ paddd m3, m6<br>
+ movu m6, [r4 + 48 + r5]<br>
+ psadbw m6, m5<br>
+ paddd m3, m6<br>
+<br>
+ mova m4, [r0 + FENC_STRIDE * 2]<br>
+ mova m5, [r0 + 16 + FENC_STRIDE * 2]<br>
+ movu m6, [r1 + r5 * 2]<br>
+ psadbw m6, m4<br>
+ paddd m0, m6<br>
+ movu m6, [r1 + 16 + r5 * 2]<br>
+ psadbw m6, m5<br>
+ paddd m0, m6<br>
+ movu m6, [r2 + r5 * 2]<br>
+ psadbw m6, m4<br>
+ paddd m1, m6<br>
+ movu m6, [r2 + 16 + r5 * 2]<br>
+ psadbw m6, m5<br>
+ paddd m1, m6<br>
+ movu m6, [r3 + r5 * 2]<br>
+ psadbw m6, m4<br>
+ paddd m2, m6<br>
+ movu m6, [r3 + 16 + r5 * 2]<br>
+ psadbw m6, m5<br>
+ paddd m2, m6<br>
+ movu m6, [r4 + r5 * 2]<br>
+ psadbw m6, m4<br>
+ paddd m3, m6<br>
+ movu m6, [r4 + 16 + r5 * 2]<br>
+ psadbw m6, m5<br>
+ paddd m3, m6<br>
+ mova m4, [r0 + 32 + FENC_STRIDE * 2]<br>
+ mova m5, [r0 + 48 + FENC_STRIDE * 2]<br>
+ movu m6, [r1 + 32 + r5 * 2]<br>
+ psadbw m6, m4<br>
+ paddd m0, m6<br>
+ movu m6, [r1 + 48 + r5 * 2]<br>
+ psadbw m6, m5<br>
+ paddd m0, m6<br>
+ movu m6, [r2 + 32 + r5 * 2]<br>
+ psadbw m6, m4<br>
+ paddd m1, m6<br>
+ movu m6, [r2 + 48 + r5 * 2]<br>
+ psadbw m6, m5<br>
+ paddd m1, m6<br>
+ movu m6, [r3 + 32 + r5 * 2]<br>
+ psadbw m6, m4<br>
+ paddd m2, m6<br>
+ movu m6, [r3 + 48 + r5 * 2]<br>
+ psadbw m6, m5<br>
+ paddd m2, m6<br>
+ movu m6, [r4 + 32 + r5 * 2]<br>
+ psadbw m6, m4<br>
+ paddd m3, m6<br>
+ movu m6, [r4 + 48 + r5 * 2]<br>
+ psadbw m6, m5<br>
+ paddd m3, m6<br>
+<br>
+ lea r0, [r0 + FENC_STRIDE * 2]<br>
+ lea r1, [r1 + r5 * 2]<br>
+ lea r2, [r2 + r5 * 2]<br>
+ lea r3, [r3 + r5 * 2]<br>
+ lea r4, [r4 + r5 * 2]<br>
+ mova m4, [r0 + FENC_STRIDE]<br>
+ mova m5, [r0 + 16 + FENC_STRIDE]<br>
+ movu m6, [r1 + r5]<br>
+ psadbw m6, m4<br>
+ paddd m0, m6<br>
+ movu m6, [r1 + 16 + r5]<br>
+ psadbw m6, m5<br>
+ paddd m0, m6<br>
+ movu m6, [r2 + r5]<br>
+ psadbw m6, m4<br>
+ paddd m1, m6<br>
+ movu m6, [r2 + 16 + r5]<br>
+ psadbw m6, m5<br>
+ paddd m1, m6<br>
+ movu m6, [r3 + r5]<br>
+ psadbw m6, m4<br>
+ paddd m2, m6<br>
+ movu m6, [r3 + 16 + r5]<br>
+ psadbw m6, m5<br>
+ paddd m2, m6<br>
+ movu m6, [r4 + r5]<br>
+ psadbw m6, m4<br>
+ paddd m3, m6<br>
+ movu m6, [r4 + 16 + r5]<br>
+ psadbw m6, m5<br>
+ paddd m3, m6<br>
+ mova m4, [r0 + 32 + FENC_STRIDE]<br>
+ mova m5, [r0 + 48 + FENC_STRIDE]<br>
+ movu m6, [r1 + 32 + r5]<br>
+ psadbw m6, m4<br>
+ paddd m0, m6<br>
+ movu m6, [r1 + 48 + r5]<br>
+ psadbw m6, m5<br>
+ paddd m0, m6<br>
+ movu m6, [r2 + 32 + r5]<br>
+ psadbw m6, m4<br>
+ paddd m1, m6<br>
+ movu m6, [r2 + 48 + r5]<br>
+ psadbw m6, m5<br>
+ paddd m1, m6<br>
+ movu m6, [r3 + 32 + r5]<br>
+ psadbw m6, m4<br>
+ paddd m2, m6<br>
+ movu m6, [r3 + 48 + r5]<br>
+ psadbw m6, m5<br>
+ paddd m2, m6<br>
+ movu m6, [r4 + 32 + r5]<br>
+ psadbw m6, m4<br>
+ paddd m3, m6<br>
+ movu m6, [r4 + 48 + r5]<br>
+ psadbw m6, m5<br>
+ paddd m3, m6<br>
+ lea r0, [r0 + FENC_STRIDE * 2]<br>
+ lea r1, [r1 + r5 * 2]<br>
+ lea r2, [r2 + r5 * 2]<br>
+ lea r3, [r3 + r5 * 2]<br>
+ lea r4, [r4 + r5 * 2]<br>
+%endmacro<br>
+<br>
;-----------------------------------------------------------------------------<br>
; void pixel_sad_x3_16x16( uint8_t *fenc, uint8_t *pix0, uint8_t *pix1,<br>
; uint8_t *pix2, intptr_t i_stride, int scores[3] )<br>
@@ -3582,6 +3806,92 @@<br>
SAD_X3_END_SSE2 1<br>
%endmacro<br>
<br>
+%macro SAD_X4_W64 0<br>
+%if ARCH_X86_64 == 1<br>
+cglobal pixel_sad_x4_64x16, 6, 8, 8<br>
+%define count r7<br>
+%else<br>
+cglobal pixel_sad_x4_64x16, 6, 7, 8, 0-4<br>
+%define count dword [rsp]<br>
+%endif<br>
+ pxor m0, m0<br>
+ pxor m1, m1<br>
+ pxor m2, m2<br>
+ pxor m3, m3<br>
+ mov count, 16<br>
+<br>
+.loop<br>
+ SAD_X4_64x4<br>
+ SAD_X4_64x4<br>
+<br>
+ sub count, 8<br>
+ jnz .loop<br>
+ SAD_X4_END_SSE2 1<br>
+<br>
+%if ARCH_X86_64 == 1<br>
+cglobal pixel_sad_x4_64x32, 6, 8, 8<br>
+%define count r7<br>
+%else<br>
+cglobal pixel_sad_x4_64x32, 6, 7, 8, 0-4<br>
+%define count dword [rsp]<br>
+%endif<br>
+ pxor m0, m0<br>
+ pxor m1, m1<br>
+ pxor m2, m2<br>
+ pxor m3, m3<br>
+ mov count, 32<br>
+<br>
+.loop<br>
+ SAD_X4_64x4<br>
+ SAD_X4_64x4<br>
+<br>
+ sub count, 8<br>
+ jnz .loop<br>
+ SAD_X4_END_SSE2 1<br>
+<br>
+%if ARCH_X86_64 == 1<br>
+cglobal pixel_sad_x4_64x48, 6, 8, 8<br>
+%define count r7<br>
+%else<br>
+cglobal pixel_sad_x4_64x48, 6, 7, 8, 0-4<br>
+%define count dword [rsp]<br>
+%endif<br>
+ pxor m0, m0<br>
+ pxor m1, m1<br>
+ pxor m2, m2<br>
+ pxor m3, m3<br>
+ mov count, 48<br>
+<br>
+.loop<br>
+ SAD_X4_64x4<br>
+ SAD_X4_64x4<br>
+<br>
+ sub count, 8<br>
+ jnz .loop<br>
+ SAD_X4_END_SSE2 1<br>
+<br>
+%if ARCH_X86_64 == 1<br>
+cglobal pixel_sad_x4_64x64, 6, 8, 8<br>
+%define count r7<br>
+%else<br>
+cglobal pixel_sad_x4_64x64, 6, 7, 8, 0-4<br>
+%define count dword [rsp]<br>
+%endif<br>
+ pxor m0, m0<br>
+ pxor m1, m1<br>
+ pxor m2, m2<br>
+ pxor m3, m3<br>
+ mov count, 64<br>
+<br>
+.loop<br>
+ SAD_X4_64x4<br>
+ SAD_X4_64x4<br>
+<br>
+ sub count, 8<br>
+ jnz .loop<br>
+ SAD_X4_END_SSE2 1<br>
+%endmacro<br>
+<br>
INIT_XMM sse2<br>
SAD_X_SSE2 3, 16, 16, 7<br>
SAD_X_SSE2 3, 16, 8, 7<br>
@@ -3629,6 +3939,7 @@<br>
SAD_X4_W24<br>
SAD_X4_W32<br>
SAD_X4_W48<br>
+SAD_X4_W64<br>
SAD_X_SSE2 4, 16, 64, 7<br>
SAD_X_SSE2 4, 16, 32, 7<br>
SAD_X_SSE2 4, 16, 16, 7<br>
@@ -3655,6 +3966,7 @@<br>
SAD_X4_W24<br>
SAD_X4_W32<br>
SAD_X4_W48<br>
+SAD_X4_W64<br>
SAD_X_SSE2 4, 16, 64, 7<br>
SAD_X_SSE2 4, 16, 32, 7<br>
SAD_X_SSE2 4, 16, 16, 7<br>
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</blockquote></div><br><br clear="all"><div><br></div>-- <br>Steve Borho
</div></div>