<div style="line-height:1.7;color:#000000;font-size:14px;font-family:arial"><DIV>At 2013-11-22 16:08:54,murugan@multicorewareinc.com wrote:<BR>># HG changeset patch<BR>># User Murugan Vairavel <murugan@multicorewareinc.com><BR>># Date 1385107712 -19800<BR>># Fri Nov 22 13:38:32 2013 +0530<BR>># Node ID 596deb572c970cf407b7f18f9b07d122487530a6<BR>># Parent 7a576d46cc9067c937677d013d70f5ed9639107b<BR>>asm: code for sse_pp_24x32 routine<BR>><BR>>diff -r 7a576d46cc90 -r 596deb572c97 source/common/x86/asm-primitives.cpp<BR>>--- a/source/common/x86/asm-primitives.cpp Fri Nov 22 13:20:33 2013 +0530<BR>>+++ b/source/common/x86/asm-primitives.cpp Fri Nov 22 13:38:32 2013 +0530<BR>>@@ -604,6 +604,7 @@<BR>> SA8D_INTER_FROM_BLOCK(sse4);<BR>> <BR>> p.sse_pp[LUMA_12x16] = x265_pixel_ssd_12x16_sse4;<BR>>+ p.sse_pp[LUMA_24x32] = x265_pixel_ssd_24x32_sse4;<BR>> <BR>> CHROMA_PIXELSUB_PS(_sse4);<BR>> <BR>>diff -r 7a576d46cc90 -r 596deb572c97 source/common/x86/pixel-a.asm<BR>>--- a/source/common/x86/pixel-a.asm Fri Nov 22 13:20:33 2013 +0530<BR>>+++ b/source/common/x86/pixel-a.asm Fri Nov 22 13:38:32 2013 +0530<BR>>@@ -482,7 +482,6 @@<BR>> SSD 32, 8<BR>> SSD 8, 32<BR>> SSD 32, 24<BR>>-SSD 24, 32<BR>> SSD 24, 24 ; not used, but resolves x265_pixel_ssd_24x24_sse2.startloop symbol<BR>> SSD 8, 4<BR>> SSD 8, 8<BR>>@@ -613,6 +612,73 @@<BR>> RET<BR>> <BR>> ;-----------------------------------------------------------------------------<BR>>+; int pixel_ssd_24x32( uint8_t *, intptr_t, uint8_t *, intptr_t )<BR>>+;-----------------------------------------------------------------------------<BR>>+INIT_XMM sse4<BR>>+cglobal pixel_ssd_24x32, 4, 7, 8, src1, stride1, src2, stride2<BR>>+<BR>>+ pxor m7, m7<BR>>+ pxor m6, m6<BR>>+ mov r4d, 16<BR>>+<BR>>+.loop<BR>>+ movu m1, [r0]<BR>>+ pmovzxbw m0, m1<BR>>+ punpckhbw m1, m6<BR>>+ movh m2, [r0 + 16]<BR>>+ pmovzxbw m2, m2<BR>>+ movu m4, [r2]<BR>>+ pmovzxbw m3, m4<BR>>+ punpckhbw m4, m6<BR>>+ movh m5, [r2 + 16]<BR>>+ pmovzxbw m5, m5<BR>pmovzxbw not need alignment acess, so we can merge it</DIV>
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<DIV>>+<BR>>+ psubw m0, m3<BR>>+ psubw m1, m4<BR>>+ psubw m2, m5<BR>>+<BR>>+ pmaddwd m0, m0<BR>>+ pmaddwd m1, m1<BR>>+ pmaddwd m2, m2<BR>>+<BR>>+ paddd m0, m1<BR>>+ paddd m7, m2<BR>>+ paddd m7, m0<BR>>+<BR>>+ movu m1, [r0 + r1]<BR>>+ pmovzxbw m0, m1<BR>>+ punpckhbw m1, m6<BR>>+ movh m2, [r0 + r1 + 16]<BR>>+ pmovzxbw m2, m2<BR>>+ movu m4, [r2 + r3]<BR>>+ pmovzxbw m3, m4<BR>>+ punpckhbw m4, m6<BR>>+ movh m5, [r2 + r3 + 16]<BR>>+ pmovzxbw m5, m5<BR>>+<BR>>+ psubw m0, m3<BR>>+ psubw m1, m4<BR>>+ psubw m2, m5<BR>>+<BR>>+ pmaddwd m0, m0<BR>>+ pmaddwd m1, m1<BR>>+ pmaddwd m2, m2<BR>>+<BR>>+ paddd m0, m1<BR>>+ paddd m7, m2<BR>>+ paddd m7, m0<BR>>+<BR>>+ dec r4d<BR>>+ lea r0, [r0 + 2 * r1]<BR>>+ lea r2, [r2 + 2 * r3]<BR>>+ jnz .loop<BR>>+<BR>>+ HADDD m7, m1<BR>>+ movd eax, m7<BR>>+<BR>>+ RET<BR>>+<BR>>+;-----------------------------------------------------------------------------<BR>> ; void pixel_ssd_nv12_core( uint16_t *pixuv1, intptr_t stride1, uint16_t *pixuv2, intptr_t stride2,<BR>> ; int width, int height, uint64_t *ssd_u, uint64_t *ssd_v )<BR>> ;<BR>>diff -r 7a576d46cc90 -r 596deb572c97 source/common/x86/pixel.h<BR>>--- a/source/common/x86/pixel.h Fri Nov 22 13:20:33 2013 +0530<BR>>+++ b/source/common/x86/pixel.h Fri Nov 22 13:38:32 2013 +0530<BR>>@@ -373,5 +373,6 @@<BR>> void x265_transpose32_sse2(pixel *dest, pixel *src, intptr_t stride);<BR>> void x265_transpose64_sse2(pixel *dest, pixel *src, intptr_t stride);<BR>> int x265_pixel_ssd_12x16_sse4(pixel *, intptr_t, pixel *, intptr_t);<BR>>+int x265_pixel_ssd_24x32_sse4(pixel *, intptr_t, pixel *, intptr_t);<BR>> <BR>> #endif // ifndef X265_I386_PIXEL_H<BR>>_______________________________________________<BR>>x265-devel mailing list<BR>>x265-devel@videolan.org<BR>>https://mailman.videolan.org/listinfo/x265-devel<BR></DIV></div>