<div dir="ltr">Re-sending the patch by correcting the alignment issue.</div><div class="gmail_extra"><br><br><div class="gmail_quote">On Tue, Nov 26, 2013 at 6:43 PM, chen <span dir="ltr"><<a href="mailto:chenm003@163.com" target="_blank">chenm003@163.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div style="line-height:1.7;font-size:14px;font-family:arial"><div>At 2013-11-26 18:45:25,<a href="mailto:yuvaraj@multicorewareinc.com" target="_blank">yuvaraj@multicorewareinc.com</a> wrote:<div>
<div class="h5"><br>># HG changeset patch<br>># User Yuvaraj Venkatesh <<a href="mailto:yuvaraj@multicorewareinc.com" target="_blank">yuvaraj@multicorewareinc.com</a>><br>># Date 1385462702 -19800<br>># Tue Nov 26 16:15:02 2013 +0530<br>
># Node ID 52738c22dce02e8d59cc4b09f1e1b23a0a8360c5<br>># Parent 116d91f08fcb123d4b088df5c1400e599306b6f8<br>>asm: assembly code for pixel_sse_ss_24x32<br>><br>>diff -r 116d91f08fcb -r 52738c22dce0 source/common/x86/asm-primitives.cpp<br>
>--- a/source/common/x86/asm-primitives.cpp Tue Nov 26 14:19:27 2013 +0800<br>>+++ b/source/common/x86/asm-primitives.cpp Tue Nov 26 16:15:02 2013 +0530<br>>@@ -103,6 +103,7 @@<br>> p.sse_ss[LUMA_16x16] = x265_pixel_ssd_ss_16x16_ ## cpu; \<br>
> p.sse_ss[LUMA_16x32] = x265_pixel_ssd_ss_16x32_ ## cpu; \<br>> p.sse_ss[LUMA_16x64] = x265_pixel_ssd_ss_16x64_ ## cpu; \<br>>+ p.sse_ss[LUMA_24x32] = x265_pixel_ssd_ss_24x32_ ## cpu; \<br>> p.sse_ss[LUMA_32x8] = x265_pixel_ssd_ss_32x8_ ## cpu; \<br>
> p.sse_ss[LUMA_32x16] = x265_pixel_ssd_ss_32x16_ ## cpu; \<br>> p.sse_ss[LUMA_32x24] = x265_pixel_ssd_ss_32x24_ ## cpu; \<br>>diff -r 116d91f08fcb -r 52738c22dce0 source/common/x86/pixel-a.asm<br>>--- a/source/common/x86/pixel-a.asm Tue Nov 26 14:19:27 2013 +0800<br>
>+++ b/source/common/x86/pixel-a.asm Tue Nov 26 16:15:02 2013 +0530<br>>@@ -469,17 +469,62 @@<br>> SSD_SS_32 64<br>> %endmacro<br>> <br>>+%macro SSD_SS_24 0<br>>+cglobal pixel_ssd_ss_24x32, 4,7,6<br>>+ FIX_STRIDES r1, r3<br>
>+ mov r4d, 16<br>>+ pxor m0, m0<br>>+.loop<br>>+ mova m1, [r0]<br>>+ psubw m1, [r2]<br></div></div>this is right, but it is unsafe, I am not sure the input pointer is alignment</div>
<div> </div>
<div><div><div class="h5">>+ pmaddwd m1, m1<br>>+ paddd m0, m1<br>>+ mova m1, [r0 + 16]<br>>+ psubw m1, [r2 + 16]<br>>+ pmaddwd m1, m1<br>>+ paddd m0, m1<br>>+ mova m1, [r0 + 32]<br>
>+ psubw m1, [r2 + 32]<br>>+ pmaddwd m1, m1<br>>+ paddd m0, m1<br>>+ lea r0, [r0 + 2*r1]<br>>+ lea r2, [r2 + 2*r3]<br>>+ mova m1, [r0]<br>>+ psubw m1, [r2]<br>
>+ pmaddwd m1, m1<br>>+ paddd m0, m1<br>>+ mova m1, [r0 + 16]<br>>+ psubw m1, [r2 + 16]<br>>+ pmaddwd m1, m1<br>>+ paddd m0, m1<br>>+ mova m1, [r0 + 32]<br>>+ psubw m1, [r2 + 32]<br>
>+ pmaddwd m1, m1<br>>+ paddd m0, m1<br>>+ lea r0, [r0 + 2*r1]<br>>+ lea r2, [r2 + 2*r3]<br>>+ dec r4d<br>>+ jnz .loop<br>>+ phaddd m0, m0<br>>+ phaddd m0, m0<br>
>+ movd eax, m0<br>>+ RET<br>>+%endmacro<br>>+<br>> INIT_XMM sse2<br>> SSD_SS_ONE<br>> SSD_SS_12x16<br>>+SSD_SS_24<br>> SSD_SS_32xN<br>> INIT_XMM sse4<br>> SSD_SS_ONE<br>> SSD_SS_12x16<br>
>+SSD_SS_24<br>> SSD_SS_32xN<br>> INIT_XMM avx<br>> SSD_SS_ONE<br>> SSD_SS_12x16<br>>+SSD_SS_24<br>> SSD_SS_32xN<br>> %endif ; !HIGH_BIT_DEPTH<br>> <br>>@@ -7696,9 +7741,6 @@<br>> %endif ; !ARCH_X86_64<br>
> %endmacro ; SA8D<br>> <br>>-;=============================================================================<br>>-; INTRA SATD<br>>-;=============================================================================<br>
> %define TRANS TRANS_SSE2<br>> %define DIFFOP DIFF_UNPACK_SSE2<br>> %define LOAD_SUMSUB_8x4P LOAD_DIFF_8x4P<br></div></div>>_______________________________________________<br>>x265-devel mailing list<br>><a href="mailto:x265-devel@videolan.org" target="_blank">x265-devel@videolan.org</a><br>
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<br></blockquote></div><br></div>