<div dir="ltr">ignore this patch.<div><br></div></div><div class="gmail_extra"><br><br><div class="gmail_quote">On Tue, Dec 3, 2013 at 1:10 PM, <span dir="ltr"><<a href="mailto:murugan@multicorewareinc.com" target="_blank">murugan@multicorewareinc.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"># HG changeset patch<br>
# User Murugan Vairavel <<a href="mailto:murugan@multicorewareinc.com">murugan@multicorewareinc.com</a>><br>
# Date 1386056379 -19800<br>
# Tue Dec 03 13:09:39 2013 +0530<br>
# Node ID 123d0c4c5683bf5c9c733830b106c538630977d8<br>
# Parent 5c2fcf4dfc981de6ede28e6b205e0d27c6d4608d<br>
asm: 10bpp code for pixel_sse_pp for 12x16, 24x32 and 64xN<br>
<br>
diff -r 5c2fcf4dfc98 -r 123d0c4c5683 source/common/x86/ssd-a.asm<br>
--- a/source/common/x86/ssd-a.asm Tue Dec 03 12:21:16 2013 +0530<br>
+++ b/source/common/x86/ssd-a.asm Tue Dec 03 13:09:39 2013 +0530<br>
@@ -109,6 +109,179 @@<br>
RET<br>
%endmacro<br>
<br>
+%macro SSD_TWO 2<br>
+cglobal pixel_ssd_ss_%1x%2, 4,7,6<br>
+ FIX_STRIDES r1, r3<br>
+ pxor m0, m0<br>
+ mov r4d, %2/2<br>
+ lea r5, [r1 * 2]<br>
+ lea r6, [r3 * 2]<br>
+.loop<br>
+ movu m1, [r0]<br>
+ movu m2, [r0 + 16]<br>
+ movu m3, [r0 + 32]<br>
+ movu m4, [r0 + 48]<br>
+ psubw m1, [r2]<br>
+ psubw m2, [r2 + 16]<br>
+ psubw m3, [r2 + 32]<br>
+ psubw m4, [r2 + 48]<br>
+ pmaddwd m1, m1<br>
+ pmaddwd m2, m2<br>
+ pmaddwd m3, m3<br>
+ pmaddwd m4, m4<br>
+ paddd m1, m2<br>
+ paddd m3, m4<br>
+ paddd m0, m1<br>
+ paddd m0, m3<br>
+ movu m1, [r0 + 64]<br>
+ movu m2, [r0 + 80]<br>
+ psubw m1, [r2 + 64]<br>
+ psubw m2, [r2 + 80]<br>
+ pmaddwd m1, m1<br>
+ pmaddwd m2, m2<br>
+ paddd m1, m2<br>
+ paddd m0, m1<br>
+%if %1 == 64<br>
+ movu m3, [r0 + 96]<br>
+ movu m4, [r0 + 112]<br>
+ psubw m3, [r2 + 96]<br>
+ psubw m4, [r2 + 112]<br>
+ pmaddwd m3, m3<br>
+ pmaddwd m4, m4<br>
+ paddd m3, m4<br>
+ paddd m0, m3<br>
+%endif<br>
+ movu m1, [r0 + r1]<br>
+ movu m2, [r0 + r1 + 16]<br>
+ movu m3, [r0 + r1 + 32]<br>
+ movu m4, [r0 + r1 + 48]<br>
+ psubw m1, [r2 + r3]<br>
+ psubw m2, [r2 + r3 + 16]<br>
+ psubw m3, [r2 + r3 + 32]<br>
+ psubw m4, [r2 + r3 + 48]<br>
+ pmaddwd m1, m1<br>
+ pmaddwd m2, m2<br>
+ pmaddwd m3, m3<br>
+ pmaddwd m4, m4<br>
+ paddd m1, m2<br>
+ paddd m3, m4<br>
+ paddd m0, m1<br>
+ paddd m0, m3<br>
+ movu m1, [r0 + r1 + 64]<br>
+ movu m2, [r0 + r1 + 80]<br>
+ psubw m1, [r2 + r3 + 64]<br>
+ psubw m2, [r2 + r3 + 80]<br>
+ pmaddwd m1, m1<br>
+ pmaddwd m2, m2<br>
+ paddd m1, m2<br>
+ paddd m0, m1<br>
+%if %1 == 64<br>
+ movu m3, [r0 + r1 + 96]<br>
+ movu m4, [r0 + r1 + 112]<br>
+ psubw m3, [r2 + r3 + 96]<br>
+ psubw m4, [r2 + r3 + 112]<br>
+ pmaddwd m3, m3<br>
+ pmaddwd m4, m4<br>
+ paddd m3, m4<br>
+ paddd m0, m3<br>
+%endif<br>
+ lea r0, [r0 + r5]<br>
+ lea r2, [r2 + r6]<br>
+ dec r4d<br>
+ jnz .loop<br>
+ HADDD m0, m5<br>
+ movd eax, xm0<br>
+ RET<br>
+%endmacro<br>
+%macro SSD_24 2<br>
+cglobal pixel_ssd_ss_%1x%2, 4,7,6<br>
+ FIX_STRIDES r1, r3<br>
+ pxor m0, m0<br>
+ mov r4d, %2/2<br>
+ lea r5, [r1 * 2]<br>
+ lea r6, [r3 * 2]<br>
+.loop<br>
+ movu m1, [r0]<br>
+ movu m2, [r0 + 16]<br>
+ movu m3, [r0 + 32]<br>
+ psubw m1, [r2]<br>
+ psubw m2, [r2 + 16]<br>
+ psubw m3, [r2 + 32]<br>
+ pmaddwd m1, m1<br>
+ pmaddwd m2, m2<br>
+ pmaddwd m3, m3<br>
+ paddd m1, m2<br>
+ paddd m0, m1<br>
+ movu m1, [r0 + r1]<br>
+ movu m2, [r0 + r1 + 16]<br>
+ movu m4, [r0 + r1 + 32]<br>
+ psubw m1, [r2 + r3]<br>
+ psubw m2, [r2 + r3 + 16]<br>
+ psubw m4, [r2 + r3 + 32]<br>
+ pmaddwd m1, m1<br>
+ pmaddwd m2, m2<br>
+ pmaddwd m4, m4<br>
+ paddd m1, m2<br>
+ paddd m3, m4<br>
+ paddd m0, m1<br>
+ paddd m0, m3<br>
+ lea r0, [r0 + r5]<br>
+ lea r2, [r2 + r6]<br>
+ dec r4d<br>
+ jnz .loop<br>
+ HADDD m0, m5<br>
+ movd eax, xm0<br>
+ RET<br>
+%endmacro<br>
+%macro SSD_12 2<br>
+cglobal pixel_ssd_ss_%1x%2, 4,7,7<br>
+ FIX_STRIDES r1, r3<br>
+ pxor m0, m0<br>
+ mov r4d, %2/4<br>
+ lea r5, [r1 * 2]<br>
+ lea r6, [r3 * 2]<br>
+.loop<br>
+ movu m1, [r0]<br>
+ movh m2, [r0 + 16]<br>
+ movu m3, [r0 + r1]<br>
+ punpcklqdq m2, [r0 + r1 + 16]<br>
+ psubw m1, [r2]<br>
+ movh m4, [r2 + 16]<br>
+ psubw m3, [r2 + r3]<br>
+ punpcklqdq m4, [r2 + r3 + 16]<br>
+ psubw m2, m4<br>
+ pmaddwd m1, m1<br>
+ pmaddwd m2, m2<br>
+ pmaddwd m3, m3<br>
+ paddd m1, m2<br>
+ paddd m0, m1<br>
+<br>
+ movu m1, [r0 + r5]<br>
+ movh m2, [r0 + r5 + 16]<br>
+ lea r0, [r0 + r5]<br>
+ movu m6, [r0 + r1]<br>
+ punpcklqdq m2, [r0 + r1 + 16]<br>
+ psubw m1, [r2 + r6]<br>
+ movh m4, [r2 + r6 + 16]<br>
+ lea r2, [r2 + r6]<br>
+ psubw m6, [r2 + r3]<br>
+ punpcklqdq m4, [r2 + r3 + 16]<br>
+ psubw m2, m4<br>
+ pmaddwd m1, m1<br>
+ pmaddwd m2, m2<br>
+ pmaddwd m6, m6<br>
+ paddd m1, m2<br>
+ paddd m3, m6<br>
+ paddd m0, m1<br>
+ paddd m0, m3<br>
+ lea r0, [r0 + r5]<br>
+ lea r2, [r2 + r6]<br>
+ dec r4d<br>
+ jnz .loop<br>
+ HADDD m0, m5<br>
+ movd eax, xm0<br>
+ RET<br>
+%endmacro<br>
INIT_MMX mmx2<br>
SSD_ONE 4, 4<br>
SSD_ONE 4, 8<br>
@@ -123,17 +296,24 @@<br>
SSD_ONE 8, 8<br>
SSD_ONE 8, 16<br>
SSD_ONE 8, 32<br>
+SSD_12 12, 16<br>
SSD_ONE 16, 4<br>
SSD_ONE 16, 8<br>
SSD_ONE 16, 12<br>
SSD_ONE 16, 16<br>
SSD_ONE 16, 32<br>
SSD_ONE 16, 64<br>
+SSD_24 24, 32<br>
SSD_ONE 32, 8<br>
SSD_ONE 32, 16<br>
SSD_ONE 32, 24<br>
SSD_ONE 32, 32<br>
SSD_ONE 32, 64<br>
+SSD_TWO 48, 64<br>
+SSD_TWO 64, 16<br>
+SSD_TWO 64, 32<br>
+SSD_TWO 64, 48<br>
+SSD_TWO 64, 64<br>
INIT_YMM avx2<br>
SSD_ONE 16, 8<br>
SSD_ONE 16, 16<br>
</blockquote></div><br><br clear="all"><div><br></div>-- <br><div dir="ltr">With Regards,<div><br></div><div>Murugan. V</div><div>+919659287478</div></div>
</div>