<div dir="ltr">The above patch is for review only.</div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Feb 25, 2015 at 2:25 PM, Divya Manivannan <span dir="ltr"><<a href="mailto:divya@multicorewareinc.com" target="_blank">divya@multicorewareinc.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"># HG changeset patch<br>
# User Divya Manivannan <<a href="mailto:divya@multicorewareinc.com">divya@multicorewareinc.com</a>><br>
# Date 1424854495 -19800<br>
# Wed Feb 25 14:24:55 2015 +0530<br>
# Node ID 34b53460c45c69a5b9e318c094c1c8c7744b4e99<br>
# Parent 02bac78bde961d60d180e59b5260fad93b98d9b4<br>
asm-avx2: filter_vpp[4x8], filter_vps[4x8]: improve 414c->289c, 353c->250c<br>
<br>
diff -r 02bac78bde96 -r 34b53460c45c source/common/x86/asm-primitives.cpp<br>
--- a/source/common/x86/asm-primitives.cpp Wed Feb 25 13:46:58 2015 +0530<br>
+++ b/source/common/x86/asm-primitives.cpp Wed Feb 25 14:24:55 2015 +0530<br>
@@ -1799,9 +1799,12 @@<br>
p.chroma[X265_CSP_I420].pu[CHROMA_420_4x4].filter_vpp = x265_interp_4tap_vert_pp_4x4_avx2;<br>
p.chroma[X265_CSP_I420].pu[CHROMA_420_8x8].filter_vpp = x265_interp_4tap_vert_pp_8x8_avx2;<br>
p.chroma[X265_CSP_I420].pu[CHROMA_420_2x4].filter_vpp = x265_interp_4tap_vert_pp_2x4_avx2;<br>
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_4x8].filter_vpp = x265_interp_4tap_vert_pp_4x8_avx2;<br>
p.chroma[X265_CSP_I420].pu[CHROMA_420_8x4].filter_vpp = x265_interp_4tap_vert_pp_8x4_avx2;<br>
+<br>
p.chroma[X265_CSP_I420].pu[CHROMA_420_2x4].filter_vps = x265_interp_4tap_vert_ps_2x4_avx2;<br>
p.chroma[X265_CSP_I420].pu[CHROMA_420_4x4].filter_vps = x265_interp_4tap_vert_ps_4x4_avx2;<br>
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_4x8].filter_vps = x265_interp_4tap_vert_ps_4x8_avx2;<br>
p.chroma[X265_CSP_I420].pu[CHROMA_420_8x4].filter_vps = x265_interp_4tap_vert_ps_8x4_avx2;<br>
p.chroma[X265_CSP_I420].pu[CHROMA_420_8x8].filter_vps = x265_interp_4tap_vert_ps_8x8_avx2;<br>
// color space i422<br>
diff -r 02bac78bde96 -r 34b53460c45c source/common/x86/ipfilter8.asm<br>
--- a/source/common/x86/ipfilter8.asm Wed Feb 25 13:46:58 2015 +0530<br>
+++ b/source/common/x86/ipfilter8.asm Wed Feb 25 14:24:55 2015 +0530<br>
@@ -2613,6 +2613,94 @@<br>
<br>
FILTER_VER_CHROMA_AVX2_4x4 pp<br>
FILTER_VER_CHROMA_AVX2_4x4 ps<br>
+<br>
+%macro FILTER_VER_CHROMA_AVX2_4x8 1<br>
+INIT_YMM avx2<br>
+cglobal interp_4tap_vert_%1_4x8, 4, 6, 5<br>
+ mov r4d, r4m<br>
+ shl r4d, 6<br>
+ sub r0, r1<br>
+<br>
+%ifdef PIC<br>
+ lea r5, [tab_ChromaCoeffVer_32]<br>
+ add r5, r4<br>
+%else<br>
+ lea r5, [tab_ChromaCoeffVer_32 + r4]<br>
+%endif<br>
+<br>
+ lea r4, [r1 * 3]<br>
+<br>
+ movd xm1, [r0]<br>
+ pinsrd xm1, [r0 + r1], 1<br>
+ pinsrd xm1, [r0 + r1 * 2], 2<br>
+ pinsrd xm1, [r0 + r4], 3 ; m1 = row[3 2 1 0]<br>
+ lea r0, [r0 + r1 * 4]<br>
+ movd xm2, [r0]<br>
+ pinsrd xm2, [r0 + r1], 1<br>
+ pinsrd xm2, [r0 + r1 * 2], 2<br>
+ pinsrd xm2, [r0 + r4], 3 ; m2 = row[7 6 5 4]<br>
+ vinserti128 m1, m1, xm2, 1 ; m1 = row[7 6 5 4 3 2 1 0]<br>
+ lea r0, [r0 + r1 * 4]<br>
+ movd xm3, [r0]<br>
+ pinsrd xm3, [r0 + r1], 1<br>
+ pinsrd xm3, [r0 + r1 * 2], 2 ; m3 = row[x 10 9 8]<br>
+ vinserti128 m2, m2, xm3, 1 ; m2 = row[x 10 9 8 7 6 5 4]<br>
+ mova m3, [interp4_vpp_shuf1]<br>
+ vpermd m0, m3, m1 ; m0 = row[4 3 3 2 2 1 1 0]<br>
+ vpermd m4, m3, m2 ; m4 = row[8 7 7 6 6 5 5 4]<br>
+ mova m3, [interp4_vpp_shuf1 + mmsize]<br>
+ vpermd m1, m3, m1 ; m1 = row[6 5 5 4 4 3 3 2]<br>
+ vpermd m2, m3, m2 ; m2 = row[10 9 9 8 8 7 7 6]<br>
+<br>
+ mova m3, [interp4_vpp_shuf]<br>
+ pshufb m0, m0, m3<br>
+ pshufb m1, m1, m3<br>
+ pshufb m2, m2, m3<br>
+ pshufb m4, m4, m3<br>
+ pmaddubsw m0, [r5]<br>
+ pmaddubsw m4, [r5]<br>
+ pmaddubsw m1, [r5 + mmsize]<br>
+ pmaddubsw m2, [r5 + mmsize]<br>
+ paddw m0, m1 ; m0 = WORD ROW[3 2 1 0]<br>
+ paddw m4, m2 ; m4 = WORD ROW[7 6 5 4]<br>
+%ifidn %1,pp<br>
+ pmulhrsw m0, [pw_512]<br>
+ pmulhrsw m4, [pw_512]<br>
+ packuswb m0, m4<br>
+ vextracti128 xm1, m0, 1<br>
+ lea r5, [r3 * 3]<br>
+ movd [r2], xm0<br>
+ pextrd [r2 + r3], xm0, 1<br>
+ movd [r2 + r3 * 2], xm1<br>
+ pextrd [r2 + r5], xm1, 1<br>
+ lea r2, [r2 + r3 * 4]<br>
+ pextrd [r2], xm0, 2<br>
+ pextrd [r2 + r3], xm0, 3<br>
+ pextrd [r2 + r3 * 2], xm1, 2<br>
+ pextrd [r2 + r5], xm1, 3<br>
+%else<br>
+ add r3d, r3d<br>
+ psubw m0, [pw_2000]<br>
+ psubw m4, [pw_2000]<br>
+ vextracti128 xm1, m0, 1<br>
+ vextracti128 xm2, m4, 1<br>
+ lea r5, [r3 * 3]<br>
+ movq [r2], xm0<br>
+ movhps [r2 + r3], xm0<br>
+ movq [r2 + r3 * 2], xm1<br>
+ movhps [r2 + r5], xm1<br>
+ lea r2, [r2 + r3 * 4]<br>
+ movq [r2], xm4<br>
+ movhps [r2 + r3], xm4<br>
+ movq [r2 + r3 * 2], xm2<br>
+ movhps [r2 + r5], xm2<br>
+%endif<br>
+ RET<br>
+%endmacro<br>
+<br>
+FILTER_VER_CHROMA_AVX2_4x8 pp<br>
+FILTER_VER_CHROMA_AVX2_4x8 ps<br>
+<br>
;-----------------------------------------------------------------------------<br>
; void interp_4tap_vert_pp_%1x%2(pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx)<br>
;-----------------------------------------------------------------------------<br>
</blockquote></div><br></div>