<div dir="ltr">please ignore this patch. I will send the updated patch.</div><div class="gmail_extra"><br><div class="gmail_quote">2015-07-29 16:33 GMT+05:30 <span dir="ltr"><<a href="mailto:rajesh@multicorewareinc.com" target="_blank">rajesh@multicorewareinc.com</a>></span>:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"># HG changeset patch<br>
# User Rajesh Paulraj<<a href="mailto:rajesh@multicorewareinc.com">rajesh@multicorewareinc.com</a>><br>
# Date 1438162042 -19800<br>
# Wed Jul 29 14:57:22 2015 +0530<br>
# Node ID 90bf2117cff7e5727c43e65f926870e8874b9ed2<br>
# Parent e08a245054434090ccb1fc1b985f955a66711157<br>
asm: avx2 code for intra_ang_16 modes 3 & 33<br>
<br>
intra_ang_16x16[ 3] - improved 1075.09->827.85<br>
intra_ang_16x16[ 33] - improved 796.68->565.86<br>
<br>
diff -r e08a24505443 -r 90bf2117cff7 source/common/x86/intrapred8.asm<br>
--- a/source/common/x86/intrapred8.asm Mon Jul 27 15:15:35 2015 +0530<br>
+++ b/source/common/x86/intrapred8.asm Wed Jul 29 14:57:22 2015 +0530<br>
@@ -13535,130 +13535,226 @@<br>
RET<br>
<br>
<br>
-INIT_YMM avx2<br>
-cglobal intra_pred_ang16_3, 3, 6, 12<br>
- mova m11, [pw_1024]<br>
- lea r5, [intra_pred_shuff_0_8]<br>
-<br>
- movu xm9, [r2 + 1 + 32]<br>
- pshufb xm9, [r5]<br>
- movu xm10, [r2 + 9 + 32]<br>
- pshufb xm10, [r5]<br>
-<br>
- movu xm7, [r2 + 8 + 32]<br>
- pshufb xm7, [r5]<br>
- vinserti128 m9, m9, xm7, 1<br>
-<br>
- movu xm8, [r2 + 16 + 32]<br>
- pshufb xm8, [r5]<br>
- vinserti128 m10, m10, xm8, 1<br>
-<br>
- lea r3, [3 * r1]<br>
- lea r4, [c_ang16_mode_3]<br>
-<br>
- INTRA_PRED_ANG16_CAL_ROW m0, m1, 0<br>
-<br>
- movu xm9, [r2 + 2 + 32]<br>
- pshufb xm9, [r5]<br>
- movu xm10, [r2 + 10 + 32]<br>
- pshufb xm10, [r5]<br>
-<br>
- movu xm7, [r2 + 9 + 32]<br>
- pshufb xm7, [r5]<br>
- vinserti128 m9, m9, xm7, 1<br>
-<br>
- movu xm8, [r2 + 17 + 32]<br>
- pshufb xm8, [r5]<br>
- vinserti128 m10, m10, xm8, 1<br>
-<br>
- INTRA_PRED_ANG16_CAL_ROW m1, m2, 1<br>
-<br>
- movu xm7, [r2 + 3 + 32]<br>
- pshufb xm7, [r5]<br>
- vinserti128 m9, m9, xm7, 0<br>
-<br>
- movu xm8, [r2 + 11 + 32]<br>
- pshufb xm8, [r5]<br>
- vinserti128 m10, m10, xm8, 0<br>
-<br>
- INTRA_PRED_ANG16_CAL_ROW m2, m3, 2<br>
-<br>
- movu xm9, [r2 + 4 + 32]<br>
- pshufb xm9, [r5]<br>
- movu xm10, [r2 + 12 + 32]<br>
- pshufb xm10, [r5]<br>
-<br>
- movu xm7, [r2 + 10 + 32]<br>
- pshufb xm7, [r5]<br>
- vinserti128 m9, m9, xm7, 1<br>
-<br>
- movu xm8, [r2 + 18 + 32]<br>
- pshufb xm8, [r5]<br>
- vinserti128 m10, m10, xm8, 1<br>
-<br>
- INTRA_PRED_ANG16_CAL_ROW m3, m4, 3<br>
-<br>
- movu xm9, [r2 + 5 + 32]<br>
- pshufb xm9, [r5]<br>
- movu xm10, [r2 + 13 + 32]<br>
- pshufb xm10, [r5]<br>
-<br>
- movu xm7, [r2 + 11 + 32]<br>
- pshufb xm7, [r5]<br>
- vinserti128 m9, m9, xm7, 1<br>
-<br>
- movu xm8, [r2 + 19 + 32]<br>
- pshufb xm8, [r5]<br>
- vinserti128 m10, m10, xm8, 1<br>
-<br>
- add r4, 4 * mmsize<br>
-<br>
- INTRA_PRED_ANG16_CAL_ROW m4, m5, 0<br>
-<br>
- movu xm7, [r2 + 12 + 32]<br>
- pshufb xm7, [r5]<br>
- vinserti128 m9, m9, xm7, 1<br>
-<br>
- movu xm8, [r2 + 20 + 32]<br>
- pshufb xm8, [r5]<br>
- vinserti128 m10, m10, xm8, 1<br>
-<br>
- INTRA_PRED_ANG16_CAL_ROW m5, m6, 1<br>
-<br>
- movu xm9, [r2 + 6 + 32]<br>
- pshufb xm9, [r5]<br>
- movu xm10, [r2 + 14 + 32]<br>
- pshufb xm10, [r5]<br>
-<br>
- movu xm7, [r2 + 13 + 32]<br>
- pshufb xm7, [r5]<br>
- vinserti128 m9, m9, xm7, 1<br>
-<br>
- movu xm8, [r2 + 21 + 32]<br>
- pshufb xm8, [r5]<br>
- vinserti128 m10, m10, xm8, 1<br>
-<br>
- INTRA_PRED_ANG16_CAL_ROW m6, m7, 2<br>
-<br>
- movu xm9, [r2 + 7 + 32]<br>
- pshufb xm9, [r5]<br>
- movu xm10, [r2 + 15 + 32]<br>
- pshufb xm10, [r5]<br>
-<br>
- movu xm7, [r2 + 14 + 32]<br>
- pshufb xm7, [r5]<br>
- vinserti128 m9, m9, xm7, 1<br>
-<br>
- movu xm8, [r2 + 22 + 32]<br>
- pshufb xm8, [r5]<br>
- vinserti128 m10, m10, xm8, 1<br>
-<br>
- INTRA_PRED_ANG16_CAL_ROW m7, m8, 3<br>
-<br>
- ; transpose and store<br>
- INTRA_PRED_TRANS_STORE_16x16<br>
- RET<br>
-<br>
+; transpose 8x32 to 16x16, used for intra_ang16x16 avx2 asm<br>
+%if ARCH_X86_64 == 1<br>
+INIT_YMM avx2<br>
+%macro TRANSPOSE_STORE_8x32 12<br>
+ jnz .mode33<br>
+<br>
+ punpcklbw m%9, m%1, m%2<br>
+ punpckhbw m%1, m%2<br>
+ punpcklbw m%10, m%3, m%4<br>
+ punpckhbw m%3, m%4<br>
+<br>
+ punpcklwd m%11, m%9, m%10<br>
+ punpckhwd m%9, m%10<br>
+ punpcklwd m%10, m%1, m%3<br>
+ punpckhwd m%1, m%3<br>
+<br>
+ punpckldq m%12, m%11, m%10<br>
+ punpckhdq m%11, m%10<br>
+ punpckldq m%10, m%9, m%1<br>
+ punpckhdq m%9, m%1<br>
+<br>
+ punpcklbw m%1, m%5, m%6<br>
+ punpckhbw m%5, m%6<br>
+ punpcklbw m%2, m%7, m%8<br>
+ punpckhbw m%7, m%8<br>
+<br>
+ punpcklwd m%3, m%1, m%2<br>
+ punpckhwd m%1, m%2<br>
+ punpcklwd m%4, m%5, m%7<br>
+ punpckhwd m%5, m%7<br>
+<br>
+ punpckldq m%2, m%3, m%4<br>
+ punpckhdq m%3, m%4<br>
+ punpckldq m%4, m%1, m%5<br>
+ punpckhdq m%1, m%5<br>
+<br>
+ punpckldq m%5, m%12, m%2<br>
+ punpckhdq m%6, m%12, m%2<br>
+ punpckldq m%7, m%10, m%4<br>
+ punpckhdq m%8, m%10, m%4<br>
+<br>
+ punpckldq m%2, m%11, m%3<br>
+ punpckhdq m%11, m%11, m%3<br>
+ punpckldq m%4, m%9, m%1<br>
+ punpckhdq m%9, m%9, m%1<br>
+<br>
+ movu [r0 + r1 * 0], xm%5<br>
+ movu [r0 + r1 * 1], xm%6<br>
+ movu [r0 + r1 * 2], xm%2<br>
+ movu [r0 + r5 * 1], xm%11<br>
+<br>
+ lea r0, [r0 + r6]<br>
+<br>
+ movu [r0 + r1 * 0], xm%7<br>
+ movu [r0 + r1 * 1], xm%8<br>
+ movu [r0 + r1 * 2], xm%4<br>
+ movu [r0 + r5 * 1], xm%9<br>
+<br>
+ lea r0, [r0 + r6]<br>
+<br>
+ vextracti128 [r0 + r1 * 0], m%5, 1<br>
+ vextracti128 [r0 + r1 * 1], m%6, 1<br>
+ vextracti128 [r0 + r1 * 2], m%2, 1<br>
+ vextracti128 [r0 + r5 * 1], m%11, 1<br>
+<br>
+ lea r0, [r0 + r6]<br>
+<br>
+ vextracti128 [r0 + r1 * 0], m%7, 1<br>
+ vextracti128 [r0 + r1 * 1], m%8, 1<br>
+ vextracti128 [r0 + r1 * 2], m%4, 1<br>
+ vextracti128 [r0 + r5 * 1], m%9, 1<br>
+ jmp .end<br>
+<br>
+.mode33:<br>
+ vpermq m%1, m%1, q3120<br>
+ vpermq m%2, m%2, q3120<br>
+ vpermq m%3, m%3, q3120<br>
+ vpermq m%4, m%4, q3120<br>
+ vpermq m%5, m%5, q3120<br>
+ vpermq m%6, m%6, q3120<br>
+ vpermq m%7, m%7, q3120<br>
+ vpermq m%8, m%8, q3120<br>
+<br>
+ movu [r0 + r1 * 0], xm%1<br>
+ movu [r0 + r1 * 1], xm%2<br>
+ movu [r0 + r1 * 2], xm%3<br>
+ movu [r0 + r5 * 1], xm%4<br>
+<br>
+ lea r0, [r0 + r6]<br>
+<br>
+ movu [r0 + r1 * 0], xm%5<br>
+ movu [r0 + r1 * 1], xm%6<br>
+ movu [r0 + r1 * 2], xm%7<br>
+ movu [r0 + r5 * 1], xm%8<br>
+<br>
+ lea r0, [r0 + r6]<br>
+<br>
+ vextracti128 [r0 + r1 * 0], m%1, 1<br>
+ vextracti128 [r0 + r1 * 1], m%2, 1<br>
+ vextracti128 [r0 + r1 * 2], m%3, 1<br>
+ vextracti128 [r0 + r5 * 1], m%4, 1<br>
+<br>
+ lea r0, [r0 + r6]<br>
+<br>
+ vextracti128 [r0 + r1 * 0], m%5, 1<br>
+ vextracti128 [r0 + r1 * 1], m%6, 1<br>
+ vextracti128 [r0 + r1 * 2], m%7, 1<br>
+ vextracti128 [r0 + r5 * 1], m%8, 1<br>
+.end:<br>
+%endmacro<br>
+<br>
+cglobal ang16_mode_3_33_row_0_15<br>
+ test r7d, r7d ; check for mode 3 or 33<br>
+ ; rows 0 to 7<br>
+ movu m0, [r2 + 1] ; [32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]<br>
+ movu m1, [r2 + 2] ; [33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2]<br>
+<br>
+ punpckhbw m2, m0, m1 ; [33 32 32 31 31 30 30 29 29 28 28 27 27 26 26 25 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]<br>
+ punpcklbw m0, m1 ; [25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]<br>
+ vextracti128 xm1, m0, 1<br>
+ vperm2i128 m0, m0, m2, 0x20 ; [17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]<br>
+ vperm2i128 m2, m2, m1, 0x20 ; [25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]<br>
+<br>
+ pmaddubsw m4, m0, [r3 + 10 * 32] ; [26]<br>
+ pmulhrsw m4, m7<br>
+<br>
+ palignr m5, m2, m0, 2<br>
+ pmaddubsw m5, [r3 + 4 * 32] ; [20]<br>
+ pmulhrsw m5, m7<br>
+<br>
+ palignr m6, m2, m0, 4<br>
+ palignr m8, m2, m0, 6<br>
+ pmaddubsw m6, [r3 - 2 * 32] ; [14]<br>
+ pmulhrsw m6, m7<br>
+ pmaddubsw m8, [r3 - 8 * 32] ; [8]<br>
+ pmulhrsw m8, m7<br>
+<br>
+ palignr m10, m2, m0, 8<br>
+ pmaddubsw m9, m10, [r3 - 14 * 32] ; [2]<br>
+ pmulhrsw m9, m7<br>
+ pmaddubsw m10, [r3 + 12 * 32] ; [28]<br>
+ pmulhrsw m10, m7<br>
+<br>
+ palignr m11, m2, m0, 10<br>
+ palignr m12, m2, m0, 12<br>
+ pmaddubsw m11, [r3 + 6 * 32] ; [22]<br>
+ pmulhrsw m11, m7<br>
+ pmaddubsw m12, [r3] ; [16]<br>
+ pmulhrsw m12, m7<br>
+<br>
+ ; rows 8 to 15<br>
+ palignr m3, m2, m0, 14<br>
+ palignr m1, m1, m2, 14<br>
+ pmaddubsw m3, [r3 - 6 * 32] ; [10]<br>
+ pmulhrsw m3, m7<br>
+ packuswb m4, m3<br>
+<br>
+ pmaddubsw m3, m2, [r3 - 12 * 32] ; [4]<br>
+ pmulhrsw m3, m7<br>
+ packuswb m5, m3<br>
+<br>
+ pmaddubsw m3, m2, [r3 + 14 * 32] ; [30]<br>
+ pmulhrsw m3, m7<br>
+ packuswb m6, m3<br>
+<br>
+ movu xm0, [r2 + 25]<br>
+ movu xm1, [r2 + 26]<br>
+ punpcklbw m0, m1<br>
+ mova m1, m2<br>
+ vinserti128 m1, m1, xm0, 0<br>
+ vpermq m1, m1, 01001110b<br>
+<br>
+ palignr m3, m1, m2, 2<br>
+ pmaddubsw m3, [r3 + 8 * 32] ; [24]<br>
+ pmulhrsw m3, m7<br>
+ packuswb m8, m3<br>
+<br>
+ palignr m3, m1, m2, 4<br>
+ pmaddubsw m3, [r3 + 2 * 32] ; [18]<br>
+ pmulhrsw m3, m7<br>
+ packuswb m9, m3<br>
+<br>
+ palignr m3, m1, m2, 6<br>
+ pmaddubsw m3, [r3 - 4 * 32] ; [12]<br>
+ pmulhrsw m3, m7<br>
+ packuswb m10, m3<br>
+<br>
+ palignr m3, m1, m2, 8<br>
+ pmaddubsw m3, [r3 - 10 * 32] ; [6]<br>
+ pmulhrsw m3, m7<br>
+ packuswb m11, m3<br>
+<br>
+ pmovzxbw m1, [r2 + 14]<br>
+ packuswb m12, m1<br>
+<br>
+ TRANSPOSE_STORE_8x32 4, 5, 6, 8, 9, 10, 11, 12, 0, 1, 2, 3<br>
+ ret<br>
+<br>
+INIT_YMM avx2<br>
+cglobal intra_pred_ang16_3, 3, 8, 13<br>
+ add r2, 32<br>
+ lea r3, [ang_table_avx2 + 16 * 32]<br>
+ lea r5, [r1 * 3] ; r5 -> 3 * stride<br>
+ lea r6, [r1 * 4] ; r6 -> 4 * stride<br>
+ mova m7, [pw_1024]<br>
+ xor r7d, r7d<br>
+<br>
+ call ang16_mode_3_33_row_0_15<br>
+ RET<br>
+<br>
+INIT_YMM avx2<br>
+cglobal intra_pred_ang16_33, 3, 8, 13<br>
+ lea r3, [ang_table_avx2 + 16 * 32]<br>
+ lea r5, [r1 * 3] ; r5 -> 3 * stride<br>
+ lea r6, [r1 * 4] ; r6 -> 4 * stride<br>
+ mova m7, [pw_1024]<br>
+<br>
+ call ang16_mode_3_33_row_0_15<br>
+ RET<br>
+%endif ; ARCH_X86_64<br>
<br>
INIT_YMM avx2<br>
cglobal intra_pred_ang16_4, 3, 6, 12<br>
@@ -14356,76 +14452,6 @@<br>
INTRA_PRED_ANG16_MC2 11<br>
INTRA_PRED_ANG16_MC3 r0 + r3, 2<br>
RET<br>
-<br>
-INIT_YMM avx2<br>
-cglobal intra_pred_ang16_33, 3, 5, 6<br>
- mova m0, [pw_1024]<br>
- mova m5, [intra_pred_shuff_0_8]<br>
- lea r3, [3 * r1]<br>
- lea r4, [c_ang16_mode_33]<br>
-<br>
- INTRA_PRED_ANG16_MC2 1<br>
- vperm2i128 m1, m1, m2, 00100000b<br>
- pmaddubsw m3, m1, [r4 + 0 * mmsize]<br>
- pmulhrsw m3, m0<br>
-<br>
- INTRA_PRED_ANG16_MC2 2<br>
- INTRA_PRED_ANG16_MC4 r0, r0 + r1, 1<br>
-<br>
- INTRA_PRED_ANG16_MC2 3<br>
- vperm2i128 m1, m1, m2, 00100000b<br>
- pmaddubsw m3, m1, [r4 + 2 * mmsize]<br>
- pmulhrsw m3, m0<br>
-<br>
- INTRA_PRED_ANG16_MC2 4<br>
- INTRA_PRED_ANG16_MC4 r0 + 2 * r1, r0 + r3, 3<br>
-<br>
- lea r0, [r0 + 4 * r1]<br>
- add r4, 4 * mmsize<br>
-<br>
- INTRA_PRED_ANG16_MC2 5<br>
- INTRA_PRED_ANG16_MC0 r0, r0 + r1, 0<br>
-<br>
- INTRA_PRED_ANG16_MC2 6<br>
- vperm2i128 m1, m1, m2, 00100000b<br>
- pmaddubsw m3, m1, [r4 + 1 * mmsize]<br>
- pmulhrsw m3, m0<br>
-<br>
- INTRA_PRED_ANG16_MC2 7<br>
- INTRA_PRED_ANG16_MC4 r0 + 2 * r1, r0 + r3, 2<br>
-<br>
- INTRA_PRED_ANG16_MC2 8<br>
- lea r0, [r0 + 4 * r1]<br>
- INTRA_PRED_ANG16_MC3 r0, 3<br>
-<br>
- INTRA_PRED_ANG16_MC2 9<br>
- add r4, 4 * mmsize<br>
- INTRA_PRED_ANG16_MC0 r0 + r1, r0 + 2 * r1, 0<br>
-<br>
- INTRA_PRED_ANG16_MC2 10<br>
- vperm2i128 m1, m1, m2, 00100000b<br>
- pmaddubsw m3, m1, [r4 + 1 * mmsize]<br>
- pmulhrsw m3, m0<br>
-<br>
- INTRA_PRED_ANG16_MC2 11<br>
- INTRA_PRED_ANG16_MC4 r0 + r3, r0 + 4 * r1, 2<br>
-<br>
- lea r0, [r0 + 4 * r1]<br>
-<br>
- INTRA_PRED_ANG16_MC2 12<br>
- vperm2i128 m1, m1, m2, 00100000b<br>
- pmaddubsw m3, m1, [r4 + 3 * mmsize]<br>
- pmulhrsw m3, m0<br>
-<br>
- INTRA_PRED_ANG16_MC2 13<br>
- INTRA_PRED_ANG16_MC4 r0 + r1, r0 + 2 * r1, 4<br>
-<br>
- add r4, 4 * mmsize<br>
-<br>
- INTRA_PRED_ANG16_MC2 14<br>
- INTRA_PRED_ANG16_MC3 r0 + r3, 1<br>
- RET<br>
-<br>
INIT_YMM avx2<br>
cglobal intra_pred_ang16_24, 3, 5, 6<br>
mova m0, [pw_1024]<br>
</blockquote></div><br></div>