<div dir="ltr"><div># HG changeset patch</div><div># User Ramya Sriraman <<a href="mailto:ramya@multicorewareinc.com">ramya@multicorewareinc.com</a>></div><div># Date 1443592336 -19800</div><div># Wed Sep 30 11:22:16 2015 +0530</div><div># Node ID ca5321eb84ef8a0e16f18a2774d3f5a299d7f997</div><div># Parent b6156a08b1def3584647f26096866c1a0c11e54a</div><div>asm: Add sse_ss for [16x16],[32x32] & [64x64] for 8bpp avx2</div><div><br></div><div>diff -r b6156a08b1de -r ca5321eb84ef source/common/x86/asm-primitives.cpp</div><div>--- a/source/common/x86/asm-primitives.cpp<span class="" style="white-space:pre"> </span>Fri Oct 09 20:45:59 2015 +0530</div><div>+++ b/source/common/x86/asm-primitives.cpp<span class="" style="white-space:pre"> </span>Wed Sep 30 11:22:16 2015 +0530</div><div>@@ -2667,6 +2667,10 @@</div><div> #if X86_64</div><div> if (cpuMask & X265_CPU_AVX2)</div><div> {</div><div>+ <a href="http://p.cu">p.cu</a>[BLOCK_16x16].sse_ss = (pixel_sse_ss_t)PFX(pixel_ssd_ss_16x16_avx2);</div><div>+ <a href="http://p.cu">p.cu</a>[BLOCK_32x32].sse_ss = (pixel_sse_ss_t)PFX(pixel_ssd_ss_32x32_avx2);</div><div>+ <a href="http://p.cu">p.cu</a>[BLOCK_64x64].sse_ss = (pixel_sse_ss_t)PFX(pixel_ssd_ss_64x64_avx2);</div><div>+</div><div> <a href="http://p.cu">p.cu</a>[BLOCK_16x16].var = PFX(pixel_var_16x16_avx2);</div><div> <a href="http://p.cu">p.cu</a>[BLOCK_32x32].var = PFX(pixel_var_32x32_avx2);</div><div> <a href="http://p.cu">p.cu</a>[BLOCK_64x64].var = PFX(pixel_var_64x64_avx2);</div><div>diff -r b6156a08b1de -r ca5321eb84ef source/common/x86/ssd-a.asm</div><div>--- a/source/common/x86/ssd-a.asm<span class="" style="white-space:pre"> </span>Fri Oct 09 20:45:59 2015 +0530</div><div>+++ b/source/common/x86/ssd-a.asm<span class="" style="white-space:pre"> </span>Wed Sep 30 11:22:16 2015 +0530</div><div>@@ -1016,8 +1016,166 @@</div><div> SSD_SS_32xN</div><div> SSD_SS_48</div><div> SSD_SS_64xN</div><div>+</div><div>+INIT_YMM avx2</div><div>+cglobal pixel_ssd_ss_16x16, 4,6,4</div><div>+ add r1d, r1d</div><div>+ add r3d, r3d</div><div>+ pxor m2, m2</div><div>+ lea r4, [3 * r1]</div><div>+ lea r5, [3 * r3]</div><div>+</div><div>+ movu m0, [r0]</div><div>+ movu m1, [r0 + r1]</div><div>+ psubw m0, [r2]</div><div>+ psubw m1, [r2 + r3]</div><div>+ pmaddwd m0, m0</div><div>+ pmaddwd m1, m1</div><div>+ paddd m3, m1, m0</div><div>+ paddd m2, m3</div><div>+</div><div>+ movu m0, [r0 + 2 * r1]</div><div>+ movu m1, [r0 + r4]</div><div>+ psubw m0, [r2 + 2 * r3]</div><div>+ psubw m1, [r2 + r5]</div><div>+ pmaddwd m0, m0</div><div>+ pmaddwd m1, m1</div><div>+ paddd m3, m1, m0</div><div>+ paddd m2, m3</div><div>+</div><div>+ lea r0, [r0 + 4 * r1]</div><div>+ lea r2, [r2 + 4 * r3]</div><div>+</div><div>+ movu m0, [r0]</div><div>+ movu m1, [r0 + r1]</div><div>+ psubw m0, [r2]</div><div>+ psubw m1, [r2 + r3]</div><div>+ pmaddwd m0, m0</div><div>+ pmaddwd m1, m1</div><div>+ paddd m3, m1, m0</div><div>+ paddd m2, m3</div><div>+</div><div>+ movu m0, [r0 + 2 * r1]</div><div>+ movu m1, [r0 + r4]</div><div>+ psubw m0, [r2 + 2 * r3]</div><div>+ psubw m1, [r2 + r5]</div><div>+ pmaddwd m0, m0</div><div>+ pmaddwd m1, m1</div><div>+ paddd m3, m1, m0</div><div>+ paddd m2, m3</div><div>+</div><div>+ lea r0, [r0 + 4 * r1]</div><div>+ lea r2, [r2 + 4 * r3]</div><div>+</div><div>+ movu m0, [r0]</div><div>+ movu m1, [r0 + r1]</div><div>+ psubw m0, [r2]</div><div>+ psubw m1, [r2 + r3]</div><div>+ pmaddwd m0, m0</div><div>+ pmaddwd m1, m1</div><div>+ paddd m3, m1, m0</div><div>+ paddd m2, m3</div><div>+</div><div>+ movu m0, [r0 + 2 * r1]</div><div>+ movu m1, [r0 + r4]</div><div>+ psubw m0, [r2 + 2 * r3]</div><div>+ psubw m1, [r2 + r5]</div><div>+ pmaddwd m0, m0</div><div>+ pmaddwd m1, m1</div><div>+ paddd m3, m1, m0</div><div>+ paddd m2, m3</div><div>+</div><div>+ lea r0, [r0 + 4 * r1]</div><div>+ lea r2, [r2 + 4 * r3]</div><div>+</div><div>+ movu m0, [r0]</div><div>+ movu m1, [r0 + r1]</div><div>+ psubw m0, [r2]</div><div>+ psubw m1, [r2 + r3]</div><div>+ pmaddwd m0, m0</div><div>+ pmaddwd m1, m1</div><div>+ paddd m3, m1, m0</div><div>+ paddd m2, m3</div><div>+</div><div>+ movu m0, [r0 + 2 * r1]</div><div>+ movu m1, [r0 + r4]</div><div>+ psubw m0, [r2 + 2 * r3]</div><div>+ psubw m1, [r2 + r5]</div><div>+ pmaddwd m0, m0</div><div>+ pmaddwd m1, m1</div><div>+ paddd m3, m1, m0</div><div>+ paddd m2, m3</div><div>+</div><div>+ HADDD m2,m0</div><div>+ movd eax, xm2</div><div>+ RET</div><div>+</div><div>+INIT_YMM avx2</div><div>+cglobal pixel_ssd_ss_32x32, 4,5,3</div><div>+ add r1d, r1d</div><div>+ add r3d, r3d</div><div>+ pxor m2, m2</div><div>+ mov r4d, 16</div><div>+.loop:</div><div>+ movu m0, [r0]</div><div>+ movu m1, [r0 + mmsize] </div><div>+ psubw m0, [r2]</div><div>+ psubw m1, [r2 + mmsize]</div><div>+ pmaddwd m0, m0</div><div>+ pmaddwd m1, m1</div><div>+ paddd m2, m0</div><div>+ paddd m2, m1</div><div>+ movu m0, [r0 + r1]</div><div>+ movu m1, [r0 + r1 + mmsize]</div><div>+ psubw m0, [r2 + r3]</div><div>+ psubw m1, [r2 + r3 + mmsize]</div><div>+ pmaddwd m0, m0</div><div>+ pmaddwd m1, m1</div><div>+ paddd m2, m0</div><div>+ paddd m2, m1</div><div>+ lea r0, [r0 + 2 * r1]</div><div>+ lea r2, [r2 + 2 * r3]</div><div>+ dec r4d</div><div>+ jne .loop</div><div>+</div><div>+ HADDD m2,m0</div><div>+ movd eax, xm2</div><div>+ RET</div><div>+INIT_YMM avx2</div><div>+cglobal pixel_ssd_ss_64x64, 4,5,3</div><div>+ add r1d, r1d</div><div>+ add r3d, r3d</div><div>+ pxor m2, m2</div><div>+ mov r4d,64</div><div>+.loop:</div><div>+ movu m0, [r0]</div><div>+ movu m1, [r0 + mmsize]</div><div>+ psubw m0, [r2]</div><div>+ psubw m1, [r2 + mmsize]</div><div>+ pmaddwd m0, m0</div><div>+ pmaddwd m1, m1</div><div>+ paddd m2, m0</div><div>+ paddd m2, m1</div><div>+ movu m0, [r0 + 2 * mmsize]</div><div>+ movu m1, [r0 + 3 * mmsize]</div><div>+ psubw m0, [r2 + 2 * mmsize]</div><div>+ psubw m1, [r2 + 3 * mmsize]</div><div>+ pmaddwd m0, m0</div><div>+ pmaddwd m1, m1</div><div>+ paddd m2, m0</div><div>+ paddd m2, m1</div><div>+</div><div>+ add r0, r1</div><div>+ add r2, r3</div><div>+</div><div>+ dec r4d</div><div>+ jne .loop</div><div>+</div><div>+ HADDD m2,m0</div><div>+ movd eax, xm2</div><div>+ RET</div><div>+</div><div> %endif ; !HIGH_BIT_DEPTH</div><div>-</div><div> %if HIGH_BIT_DEPTH == 0</div><div> %macro SSD_LOAD_FULL 5</div><div> movu m1, [t0+%1]</div><div><br></div></div><div class="gmail_extra"><br clear="all"><div><div class="gmail_signature"><div dir="ltr"><div><div dir="ltr"><div><div><span style="color:rgb(56,118,29)"><br></span></div><div><span style="color:rgb(56,118,29)">Thank you<br></span></div><span style="color:rgb(56,118,29)">Regards<br></span></div><span style="color:rgb(56,118,29)">Ramya</span><br></div></div></div></div></div>
<br><div class="gmail_quote">On Mon, Oct 12, 2015 at 9:37 AM, chen <span dir="ltr"><<a href="mailto:chenm003@163.com" target="_blank">chenm003@163.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div style="line-height:1.7;color:#000000;font-size:14px;font-family:arial"><pre><div><div class="h5"><br>At 2015-10-12 11:58:46,<a href="mailto:ramya@multicorewareinc.com" target="_blank">ramya@multicorewareinc.com</a> wrote:
># HG changeset patch
># User Ramya Sriraman <<a href="mailto:ramya@multicorewareinc.com" target="_blank">ramya@multicorewareinc.com</a>>
># Date 1443592336 -19800
># Wed Sep 30 11:22:16 2015 +0530
># Node ID f0d43eb655f0048fe5dd491ee4ad1c0d304b76f8
># Parent b6156a08b1def3584647f26096866c1a0c11e54a
>asm: Add sse_ss for [16x16],[32x32] & [64x64] for 8bpp avx2
>
>diff -r b6156a08b1de -r f0d43eb655f0 source/common/x86/asm-primitives.cpp
>--- a/source/common/x86/asm-primitives.cpp Fri Oct 09 20:45:59 2015 +0530
>+++ b/source/common/x86/asm-primitives.cpp Wed Sep 30 11:22:16 2015 +0530
>@@ -2667,6 +2667,10 @@
> #if X86_64
> if (cpuMask & X265_CPU_AVX2)
> {
>+ <a href="http://p.cu" target="_blank">p.cu</a>[BLOCK_16x16].sse_ss = (pixel_sse_ss_t)PFX(pixel_ssd_ss_16x16_avx2);
>+ <a href="http://p.cu" target="_blank">p.cu</a>[BLOCK_32x32].sse_ss = (pixel_sse_ss_t)PFX(pixel_ssd_ss_32x32_avx2);
>+ <a href="http://p.cu" target="_blank">p.cu</a>[BLOCK_64x64].sse_ss = (pixel_sse_ss_t)PFX(pixel_ssd_ss_64x64_avx2);
>+
> <a href="http://p.cu" target="_blank">p.cu</a>[BLOCK_16x16].var = PFX(pixel_var_16x16_avx2);
> <a href="http://p.cu" target="_blank">p.cu</a>[BLOCK_32x32].var = PFX(pixel_var_32x32_avx2);
> <a href="http://p.cu" target="_blank">p.cu</a>[BLOCK_64x64].var = PFX(pixel_var_64x64_avx2);
>diff -r b6156a08b1de -r f0d43eb655f0 source/common/x86/ssd-a.asm
>--- a/source/common/x86/ssd-a.asm Fri Oct 09 20:45:59 2015 +0530
>+++ b/source/common/x86/ssd-a.asm Wed Sep 30 11:22:16 2015 +0530
>@@ -1016,8 +1016,171 @@
> SSD_SS_32xN
> SSD_SS_48
> SSD_SS_64xN
>+
>+INIT_YMM avx2
>+cglobal pixel_ssd_ss_16x16, 4,4,3
>+ add r1d, r1d
>+ add r3d, r3d
>+ pxor m2, m2
>+
>+ movu m0, [r0]
>+ movu m1, [r0 + r1]
>+ psubw m0, [r2]
>+ psubw m1, [r2 + r3]
>+ lea r0, [r0 + 2 * r1]
>+ lea r2, [r2 + 2 * r3]<br></div></div>we have more register to buffer r1*3, it will reduce number of LEA<span class=""><br>
>+ pmaddwd m0, m0
>+ pmaddwd m1, m1
>+ paddd m2, m1
>+ paddd m2, m0<br></span>use m2 and m3 for partial sum, it may broken long dependency link
</pre></div><br>_______________________________________________<br>
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<br></blockquote></div><br></div>