<div dir="ltr"><div># HG changeset patch</div><div># User Ramya Sriraman <<a href="mailto:ramya@multicorewareinc.com">ramya@multicorewareinc.com</a>></div><div># Date 1443592336 -19800</div><div># Wed Sep 30 11:22:16 2015 +0530</div><div># Node ID 4f3b58b4db8d6f10ec849ad9f2ab9be3cf12649a</div><div># Parent b6156a08b1def3584647f26096866c1a0c11e54a</div><div>asm: Add sse_ss for [16x16],[32x32] & [64x64] for 8bpp avx2</div><div><br></div><div>diff -r b6156a08b1de -r 4f3b58b4db8d source/common/x86/asm-primitives.cpp</div><div>--- a/source/common/x86/asm-primitives.cpp<span class="" style="white-space:pre"> </span>Fri Oct 09 20:45:59 2015 +0530</div><div>+++ b/source/common/x86/asm-primitives.cpp<span class="" style="white-space:pre"> </span>Wed Sep 30 11:22:16 2015 +0530</div><div>@@ -2667,6 +2667,10 @@</div><div> #if X86_64</div><div> if (cpuMask & X265_CPU_AVX2)</div><div> {</div><div>+ <a href="http://p.cu">p.cu</a>[BLOCK_16x16].sse_ss = (pixel_sse_ss_t)PFX(pixel_ssd_ss_16x16_avx2);</div><div>+ <a href="http://p.cu">p.cu</a>[BLOCK_32x32].sse_ss = (pixel_sse_ss_t)PFX(pixel_ssd_ss_32x32_avx2);</div><div>+ <a href="http://p.cu">p.cu</a>[BLOCK_64x64].sse_ss = (pixel_sse_ss_t)PFX(pixel_ssd_ss_64x64_avx2);</div><div>+</div><div> <a href="http://p.cu">p.cu</a>[BLOCK_16x16].var = PFX(pixel_var_16x16_avx2);</div><div> <a href="http://p.cu">p.cu</a>[BLOCK_32x32].var = PFX(pixel_var_32x32_avx2);</div><div> <a href="http://p.cu">p.cu</a>[BLOCK_64x64].var = PFX(pixel_var_64x64_avx2);</div><div>diff -r b6156a08b1de -r 4f3b58b4db8d source/common/x86/ssd-a.asm</div><div>--- a/source/common/x86/ssd-a.asm<span class="" style="white-space:pre"> </span>Fri Oct 09 20:45:59 2015 +0530</div><div>+++ b/source/common/x86/ssd-a.asm<span class="" style="white-space:pre"> </span>Wed Sep 30 11:22:16 2015 +0530</div><div>@@ -1016,6 +1016,172 @@</div><div> SSD_SS_32xN</div><div> SSD_SS_48</div><div> SSD_SS_64xN</div><div>+</div><div>+INIT_YMM avx2</div><div>+cglobal pixel_ssd_ss_16x16, 4,6,4</div><div>+ add r1d, r1d</div><div>+ add r3d, r3d</div><div>+ pxor m2, m2</div><div>+ pxor m3, m3</div><div>+ lea r4, [3 * r1]</div><div>+ lea r5, [3 * r3]</div><div>+</div><div>+ movu m0, [r0]</div><div>+ movu m1, [r0 + r1]</div><div>+ psubw m0, [r2]</div><div>+ psubw m1, [r2 + r3]</div><div>+ pmaddwd m0, m0</div><div>+ pmaddwd m1, m1</div><div>+ paddd m2, m0</div><div>+ paddd m3, m1</div><div>+</div><div>+ movu m0, [r0 + 2 * r1]</div><div>+ movu m1, [r0 + r4]</div><div>+ psubw m0, [r2 + 2 * r3]</div><div>+ psubw m1, [r2 + r5]</div><div>+ pmaddwd m0, m0</div><div>+ pmaddwd m1, m1</div><div>+ paddd m2, m0</div><div>+ paddd m3, m1</div><div>+</div><div>+ lea r0, [r0 + 4 * r1]</div><div>+ lea r2, [r2 + 4 * r3]</div><div>+</div><div>+ movu m0, [r0]</div><div>+ movu m1, [r0 + r1]</div><div>+ psubw m0, [r2]</div><div>+ psubw m1, [r2 + r3]</div><div>+ pmaddwd m0, m0</div><div>+ pmaddwd m1, m1</div><div>+ paddd m2, m0</div><div>+ paddd m3, m1</div><div>+</div><div>+ movu m0, [r0 + 2 * r1]</div><div>+ movu m1, [r0 + r4]</div><div>+ psubw m0, [r2 + 2 * r3]</div><div>+ psubw m1, [r2 + r5]</div><div>+ pmaddwd m0, m0</div><div>+ pmaddwd m1, m1</div><div>+ paddd m2, m0</div><div>+ paddd m3, m1</div><div>+</div><div>+ lea r0, [r0 + 4 * r1]</div><div>+ lea r2, [r2 + 4 * r3]</div><div>+</div><div>+ movu m0, [r0]</div><div>+ movu m1, [r0 + r1]</div><div>+ psubw m0, [r2]</div><div>+ psubw m1, [r2 + r3]</div><div>+ pmaddwd m0, m0</div><div>+ pmaddwd m1, m1</div><div>+ paddd m2, m0</div><div>+ paddd m3, m1</div><div>+</div><div>+ movu m0, [r0 + 2 * r1]</div><div>+ movu m1, [r0 + r4]</div><div>+ psubw m0, [r2 + 2 * r3]</div><div>+ psubw m1, [r2 + r5]</div><div>+ pmaddwd m0, m0</div><div>+ pmaddwd m1, m1</div><div>+ paddd m2, m0</div><div>+ paddd m3, m1</div><div>+</div><div>+ lea r0, [r0 + 4 * r1]</div><div>+ lea r2, [r2 + 4 * r3]</div><div>+</div><div>+ movu m0, [r0]</div><div>+ movu m1, [r0 + r1]</div><div>+ psubw m0, [r2]</div><div>+ psubw m1, [r2 + r3]</div><div>+ pmaddwd m0, m0</div><div>+ pmaddwd m1, m1</div><div>+ paddd m2, m0</div><div>+ paddd m3, m1</div><div>+</div><div>+ movu m0, [r0 + 2 * r1]</div><div>+ movu m1, [r0 + r4]</div><div>+ psubw m0, [r2 + 2 * r3]</div><div>+ psubw m1, [r2 + r5]</div><div>+ pmaddwd m0, m0</div><div>+ pmaddwd m1, m1</div><div>+ paddd m2, m0</div><div>+ paddd m3, m1</div><div>+</div><div>+ paddd m2, m3</div><div>+ HADDD m2, m0</div><div>+ movd eax, xm2</div><div>+ RET</div><div>+</div><div>+INIT_YMM avx2</div><div>+cglobal pixel_ssd_ss_32x32, 4,5,4</div><div>+ add r1d, r1d</div><div>+ add r3d, r3d</div><div>+ pxor m2, m2</div><div>+ pxor m3, m3</div><div>+ mov r4d, 16</div><div>+.loop:</div><div>+ movu m0, [r0]</div><div>+ movu m1, [r0 + mmsize] </div><div>+ psubw m0, [r2]</div><div>+ psubw m1, [r2 + mmsize]</div><div>+ pmaddwd m0, m0</div><div>+ pmaddwd m1, m1</div><div>+ paddd m2, m0</div><div>+ paddd m3, m1</div><div>+ movu m0, [r0 + r1]</div><div>+ movu m1, [r0 + r1 + mmsize]</div><div>+ psubw m0, [r2 + r3]</div><div>+ psubw m1, [r2 + r3 + mmsize]</div><div>+ pmaddwd m0, m0</div><div>+ pmaddwd m1, m1</div><div>+ paddd m2, m0</div><div>+ paddd m3, m1</div><div>+ lea r0, [r0 + 2 * r1]</div><div>+ lea r2, [r2 + 2 * r3]</div><div>+ dec r4d</div><div>+ jne .loop</div><div>+</div><div>+ paddd m2, m3</div><div>+ HADDD m2, m0</div><div>+ movd eax, xm2</div><div>+ RET</div><div>+</div><div>+INIT_YMM avx2</div><div>+cglobal pixel_ssd_ss_64x64, 4,5,4</div><div>+ add r1d, r1d</div><div>+ add r3d, r3d</div><div>+ pxor m2, m2</div><div>+ pxor m3, m3</div><div>+ mov r4d,64</div><div>+.loop:</div><div>+ movu m0, [r0]</div><div>+ movu m1, [r0 + mmsize]</div><div>+ psubw m0, [r2]</div><div>+ psubw m1, [r2 + mmsize]</div><div>+ pmaddwd m0, m0</div><div>+ pmaddwd m1, m1</div><div>+ paddd m2, m0</div><div>+ paddd m3, m1</div><div>+ movu m0, [r0 + 2 * mmsize]</div><div>+ movu m1, [r0 + 3 * mmsize]</div><div>+ psubw m0, [r2 + 2 * mmsize]</div><div>+ psubw m1, [r2 + 3 * mmsize]</div><div>+ pmaddwd m0, m0</div><div>+ pmaddwd m1, m1</div><div>+ paddd m2, m0</div><div>+ paddd m3, m1</div><div>+</div><div>+ add r0, r1</div><div>+ add r2, r3</div><div>+</div><div>+ dec r4d</div><div>+ jne .loop</div><div>+</div><div>+ paddd m2, m3</div><div>+ HADDD m2, m0</div><div>+ movd eax, xm2</div><div>+ RET</div><div>+</div><div> %endif ; !HIGH_BIT_DEPTH</div><div> </div><div> %if HIGH_BIT_DEPTH == 0</div><div><br></div></div><div class="gmail_extra"><br clear="all"><div><div class="gmail_signature"><div dir="ltr"><div><div dir="ltr"><div><div><span style="color:rgb(56,118,29)"><br></span></div><div><span style="color:rgb(56,118,29)">Thank you<br></span></div><span style="color:rgb(56,118,29)">Regards<br></span></div><span style="color:rgb(56,118,29)">Ramya</span><br></div></div></div></div></div>
<br><div class="gmail_quote">On Mon, Oct 12, 2015 at 7:52 PM, chen <span dir="ltr"><<a href="mailto:chenm003@163.com" target="_blank">chenm003@163.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div style="line-height:1.7;color:#000000;font-size:14px;font-family:arial"><span class=""><div><br></div><div></div><div></div><div><br></div>At 2015-10-12 14:23:41,"Ramya Sriraman" <<a href="mailto:ramya@multicorewareinc.com" target="_blank">ramya@multicorewareinc.com</a>> wrote:<br> </span><blockquote style="margin:0px 0px 0px 0.8ex;padding-left:1ex;border-left-color:rgb(204,204,204);border-left-width:1px;border-left-style:solid"><div dir="ltr"><span class=""><div># HG changeset patch</div><div># User Ramya Sriraman <<a href="mailto:ramya@multicorewareinc.com" target="_blank">ramya@multicorewareinc.com</a>></div><div># Date 1443592336 -19800</div><div># Wed Sep 30 11:22:16 2015 +0530</div></span><div><div class="h5"><div># Node ID ca5321eb84ef8a0e16f18a2774d3f5a299d7f997</div><div># Parent b6156a08b1def3584647f26096866c1a0c11e54a</div><div>asm: Add sse_ss for [16x16],[32x32] & [64x64] for 8bpp avx2</div><div><br></div><div>diff -r b6156a08b1de -r ca5321eb84ef source/common/x86/asm-primitives.cpp</div><div>--- a/source/common/x86/asm-primitives.cpp<span style="white-space:pre-wrap"> </span>Fri Oct 09 20:45:59 2015 +0530</div><div>+++ b/source/common/x86/asm-primitives.cpp<span style="white-space:pre-wrap"> </span>Wed Sep 30 11:22:16 2015 +0530</div><div>@@ -2667,6 +2667,10 @@</div><div> #if X86_64</div><div> if (cpuMask & X265_CPU_AVX2)</div><div> {</div><div>+ <a href="http://p.cu" target="_blank">p.cu</a>[BLOCK_16x16].sse_ss = (pixel_sse_ss_t)PFX(pixel_ssd_ss_16x16_avx2);</div><div>+ <a href="http://p.cu" target="_blank">p.cu</a>[BLOCK_32x32].sse_ss = (pixel_sse_ss_t)PFX(pixel_ssd_ss_32x32_avx2);</div><div>+ <a href="http://p.cu" target="_blank">p.cu</a>[BLOCK_64x64].sse_ss = (pixel_sse_ss_t)PFX(pixel_ssd_ss_64x64_avx2);</div><div>+</div><div> <a href="http://p.cu" target="_blank">p.cu</a>[BLOCK_16x16].var = PFX(pixel_var_16x16_avx2);</div><div> <a href="http://p.cu" target="_blank">p.cu</a>[BLOCK_32x32].var = PFX(pixel_var_32x32_avx2);</div><div> <a href="http://p.cu" target="_blank">p.cu</a>[BLOCK_64x64].var = PFX(pixel_var_64x64_avx2);</div><div>diff -r b6156a08b1de -r ca5321eb84ef source/common/x86/ssd-a.asm</div><div>--- a/source/common/x86/ssd-a.asm<span style="white-space:pre-wrap"> </span>Fri Oct 09 20:45:59 2015 +0530</div><div>+++ b/source/common/x86/ssd-a.asm<span style="white-space:pre-wrap"> </span>Wed Sep 30 11:22:16 2015 +0530</div><div>@@ -1016,8 +1016,166 @@</div><div> SSD_SS_32xN</div><div> SSD_SS_48</div><div> SSD_SS_64xN</div><div>+</div><div>+INIT_YMM avx2</div><div>+cglobal pixel_ssd_ss_16x16, 4,6,4</div><div>+ add r1d, r1d</div><div>+ add r3d, r3d</div><div>+ pxor m2, m2</div><div>+ lea r4, [3 * r1]</div><div>+ lea r5, [3 * r3]</div><div>+</div><div>+ movu m0, [r0]</div><div>+ movu m1, [r0 + r1]</div><div>+ psubw m0, [r2]</div><div>+ psubw m1, [r2 + r3]</div><div>+ pmaddwd m0, m0</div><div>+ pmaddwd m1, m1</div><div>+ paddd m3, m1, m0</div><div>+ paddd m2, m3</div><div>+</div><div>+ movu m0, [r0 + 2 * r1]</div><div>+ movu m1, [r0 + r4]</div><div>+ psubw m0, [r2 + 2 * r3]</div><div>+ psubw m1, [r2 + r5]</div><div>+ pmaddwd m0, m0</div><div>+ pmaddwd m1, m1</div><div>+ paddd m3, m1, m0</div></div></div><div>+ paddd m2, m3<br>paddd m2, m0<br>paddd m3, m1<br><br></div><div><div class="h5"><div>+</div><div>+ lea r0, [r0 + 4 * r1]</div><div>+ lea r2, [r2 + 4 * r3]</div><div>+</div><div>+ movu m0, [r0]</div><div>+ movu m1, [r0 + r1]</div><div>+ psubw m0, [r2]</div><div>+ psubw m1, [r2 + r3]</div><div>+ pmaddwd m0, m0</div><div>+ pmaddwd m1, m1</div><div>+ paddd m3, m1, m0</div><div>+ paddd m2, m3</div><div>+</div><div>+ movu m0, [r0 + 2 * r1]</div><div>+ movu m1, [r0 + r4]</div><div>+ psubw m0, [r2 + 2 * r3]</div><div>+ psubw m1, [r2 + r5]</div><div>+ pmaddwd m0, m0</div><div>+ pmaddwd m1, m1</div><div>+ paddd m3, m1, m0</div><div>+ paddd m2, m3</div><div>+</div><div>+ lea r0, [r0 + 4 * r1]</div><div>+ lea r2, [r2 + 4 * r3]</div><div>+</div><div>+ movu m0, [r0]</div><div>+ movu m1, [r0 + r1]</div><div>+ psubw m0, [r2]</div><div>+ psubw m1, [r2 + r3]</div><div>+ pmaddwd m0, m0</div><div>+ pmaddwd m1, m1</div><div>+ paddd m3, m1, m0</div><div>+ paddd m2, m3</div><div>+</div><div>+ movu m0, [r0 + 2 * r1]</div><div>+ movu m1, [r0 + r4]</div><div>+ psubw m0, [r2 + 2 * r3]</div><div>+ psubw m1, [r2 + r5]</div><div>+ pmaddwd m0, m0</div><div>+ pmaddwd m1, m1</div><div>+ paddd m3, m1, m0</div><div>+ paddd m2, m3</div><div>+</div><div>+ lea r0, [r0 + 4 * r1]</div><div>+ lea r2, [r2 + 4 * r3]</div><div>+</div><div>+ movu m0, [r0]</div><div>+ movu m1, [r0 + r1]</div><div>+ psubw m0, [r2]</div><div>+ psubw m1, [r2 + r3]</div><div>+ pmaddwd m0, m0</div><div>+ pmaddwd m1, m1</div><div>+ paddd m3, m1, m0</div><div>+ paddd m2, m3</div><div>+</div><div>+ movu m0, [r0 + 2 * r1]</div><div>+ movu m1, [r0 + r4]</div><div>+ psubw m0, [r2 + 2 * r3]</div><div>+ psubw m1, [r2 + r5]</div><div>+ pmaddwd m0, m0</div><div>+ pmaddwd m1, m1</div><div>+ paddd m3, m1, m0</div><div>+ paddd m2, m3</div><div>+</div><div>+ HADDD m2,m0</div><div>+ movd eax, xm2</div><div>+ RET</div><div>+</div><div>+INIT_YMM avx2</div><div>+cglobal pixel_ssd_ss_32x32, 4,5,3</div><div>+ add r1d, r1d</div><div>+ add r3d, r3d</div><div>+ pxor m2, m2</div><div>+ mov r4d, 16</div><div>+.loop:</div><div>+ movu m0, [r0]</div><div>+ movu m1, [r0 + mmsize] </div><div>+ psubw m0, [r2]</div><div>+ psubw m1, [r2 + mmsize]</div><div>+ pmaddwd m0, m0</div><div>+ pmaddwd m1, m1</div><div>+ paddd m2, m0</div><div>+ paddd m2, m1</div><div>+ movu m0, [r0 + r1]</div><div>+ movu m1, [r0 + r1 + mmsize]</div><div>+ psubw m0, [r2 + r3]</div><div>+ psubw m1, [r2 + r3 + mmsize]</div><div>+ pmaddwd m0, m0</div><div>+ pmaddwd m1, m1</div><div>+ paddd m2, m0</div><div>+ paddd m2, m1</div><div>+ lea r0, [r0 + 2 * r1]</div><div>+ lea r2, [r2 + 2 * r3]</div><div>+ dec r4d</div><div>+ jne .loop</div><div>+</div><div>+ HADDD m2,m0</div><div>+ movd eax, xm2</div></div></div><div>+ RET<br>need empty line in between two functions</div><span class=""><div><br></div><div>+INIT_YMM avx2</div><div>+cglobal pixel_ssd_ss_64x64, 4,5,3</div><div>+ add r1d, r1d</div><div>+ add r3d, r3d</div><div>+ pxor m2, m2</div><div>+ mov r4d,64</div><div>+.loop:</div><div>+ movu m0, [r0]</div><div>+ movu m1, [r0 + mmsize]</div><div>+ psubw m0, [r2]</div><div>+ psubw m1, [r2 + mmsize]</div><div>+ pmaddwd m0, m0</div><div>+ pmaddwd m1, m1</div><div>+ paddd m2, m0</div><div>+ paddd m2, m1</div><div>+ movu m0, [r0 + 2 * mmsize]</div><div>+ movu m1, [r0 + 3 * mmsize]</div><div>+ psubw m0, [r2 + 2 * mmsize]</div><div>+ psubw m1, [r2 + 3 * mmsize]</div><div>+ pmaddwd m0, m0</div><div>+ pmaddwd m1, m1</div><div>+ paddd m2, m0</div></span><div>+ paddd m2, m1<br>paddd m2/m3<br><br></div></div></blockquote></div><br>_______________________________________________<br>
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