<div style="line-height:1.7;color:#000000;font-size:14px;font-family:Arial"><div id="spnEditorContent"><p style="margin: 0;">Hi Hari,</p><p style="margin: 0;"><br></p><p style="margin: 0;">Thank you for your information.</p><p style="margin: 0;">My A77 document looks older, it does not show uOps, so we can keep your LDR+ADD in patch, thanks.</p><p style="margin: 0;"><br></p></div><div style="position:relative;zoom:1"></div><div id="divNeteaseMailCard"></div><div style="margin: 0;">Regards,</div><div style="margin: 0;">Chen</div><pre><br>At 2024-05-29 19:24:16, "Hari Limaye" <hari.limaye@arm.com> wrote:
>Hi Chen,
>
>Thank you for clarifying.
>
>From the Arm CPU Software Optimisation Guides, LD1R requires an extra micro-op for the broadcast compared to the regular load (LDR). Benchmarking shows that using LD1R in the sad functions of width 4 is ~20% slower than using the LDR, ADD sequence.
>
>Many thanks,
>
>Hari
</pre></div>