<div data-ntes="ntes_mail_body_root" style="line-height:1.7;color:#000000;font-size:14px;font-family:Arial"><div id="spnEditorContent"><p style="margin: 0;">Hi Gerda,</p><p style="margin: 0;"><br></p><p style="margin: 0;">Thank for the explain.</p><p style="margin: 0;">LDP give more bandwidth in most ARM CPU, the extra ADD instruction may execute parallelism in pipeline, so it may faster.</p><p style="margin: 0;">However, in this function, the affect is small, we can keep your code.</p><p style="margin: 0;"><br></p><p style="margin: 0;">Regards,</p><p style="margin: 0;">Chen</p><p style="margin: 0;"><br></p></div><p>At 2024-12-14 00:06:12, "Gerda Zsejke More" <GerdaZsejke.More@arm.com> wrote:</p><blockquote id="isReplyContent" style="PADDING-LEFT: 1ex; MARGIN: 0px 0px 0px 0.8ex; BORDER-LEFT: #ccc 1px solid"><div xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns:m="http://schemas.microsoft.com/office/2004/12/omml">
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<p class="MsoNormal">Hi Chen,</p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">LD1 was used here because LDP can<span lang="EN-US">กฏ</span>t post increment the x0 and x2 registers (we are loading into two registers, but the same applies to LDR as well).
<span lang="EN-US"><br>
</span>We would need a separate ADD instruction after the load, and this performs the same as the existing code.</p>
<p class="MsoNormal"><span lang="EN-US"><br>
Thanks,<br>
Gerda<br>
<br>
<br>
> </span>Thank for the patches, I have some comments</p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><span lang="EN-US">> </span>* In current version, we support pixel up to 12 bits, so sse_pp equal to sse_ss, of course, separate 16-bits version is not bad idea.</p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><span lang="EN-US">> </span>* In below code, LD1 vs LDR, which one better?</p>
<p class="MsoNormal"><span lang="EN-US">> </span>+ ld1 {v16.8h-v17.8h}, [x0], x1</p>
<p class="MsoNormal"><span lang="EN-US">> </span>+ ld1 {v18.8h-v19.<span lang="EN-US"><br>
<br>
</span>At 2024-12-10 23:59:15, "Gerda Zsejke More" <<a href="https://mailman.videolan.org/listinfo/x265-devel">gerdazsejke.more at arm.com</a>> wrote:</p>
<p class="MsoNormal">><i>Hi,<o:p></o:p></i></p>
<p class="MsoNormal">><i><o:p> </o:p></i></p>
<p class="MsoNormal">><i>This patch series adds Neon and SVE asm implementation of HBD SSE_PP, SSE_SS and SSD_S functions.<o:p></o:p></i></p>
<p class="MsoNormal">><i>The added HBD SSE_SS and SSD_S SVE implementation is suitable for SBD as well, so enable it for that.<o:p></o:p></i></p>
<p class="MsoNormal">><i>Delete unused Neon intrinsics functions for SSE and SSD_S.<o:p></o:p></i></p>
<p class="MsoNormal">><i><o:p> </o:p></i></p>
<p class="MsoNormal">><i>This series is based on the master branch.<o:p></o:p></i></p>
<p class="MsoNormal">><i><o:p> </o:p></i></p>
<p class="MsoNormal">><i>Many thanks,<o:p></o:p></i></p>
<p class="MsoNormal">><i>Gerda<o:p></o:p></i></p>
<p class="MsoNormal">><i><o:p> </o:p></i></p>
<p class="MsoNormal">><i>Gerda Zsejke More (11):<o:p></o:p></i></p>
<p class="MsoNormal">><i> Avoid aliasing HBD SSE_PP functions for AArch64 platforms<o:p></o:p></i></p>
<p class="MsoNormal">><i> AArch64: Add Neon asm implementation of HBD SSE_PP<o:p></o:p></i></p>
<p class="MsoNormal">><i> AArch64: Add SVE asm implementation of HBD SSE_PP<o:p></o:p></i></p>
<p class="MsoNormal">><i> AArch64: Add Neon asm implementation of HBD SSE_SS<o:p></o:p></i></p>
<p class="MsoNormal">><i> AArch64: Add SVE asm implementation of HBD SSE_SS<o:p></o:p></i></p>
<p class="MsoNormal">><i> AArch64: Enable existing SSE_SS SVE impl for SBD<o:p></o:p></i></p>
<p class="MsoNormal">><i> AArch64: Delete sse_neon implementation<o:p></o:p></i></p>
<p class="MsoNormal">><i> AArch64: Add Neon asm implementation of HBD SSD_S<o:p></o:p></i></p>
<p class="MsoNormal">><i> AArch64: Add SVE asm implementation of HBD SSD_S<o:p></o:p></i></p>
<p class="MsoNormal">><i> AArch64: Enable existing SSD_S SVE impl for SBD<o:p></o:p></i></p>
<p class="MsoNormal">><i> AArch64: Delete pixel_ssd_s_neon implementation<o:p></o:p></i></p>
<p class="MsoNormal">><i><o:p> </o:p></i></p>
<p class="MsoNormal">><i> source/common/CMakeLists.txt | 4 +-<o:p></o:p></i></p>
<p class="MsoNormal">><i> source/common/aarch64/asm-primitives.cpp | 84 +--<o:p></o:p></i></p>
<p class="MsoNormal">><i> source/common/aarch64/pixel-prim.cpp | 89 ----<o:p></o:p></i></p>
<p class="MsoNormal">><i> source/common/aarch64/ssd-a-sve.S | 483 +++++++++++++++++<o:p></o:p></i></p>
<p class="MsoNormal">><i> source/common/aarch64/ssd-a-sve2.S | 626 -----------------------<o:p></o:p></i></p>
<p class="MsoNormal">><i> source/common/aarch64/ssd-a.S | 525 +++++++++++++++++++<o:p></o:p></i></p>
<p class="MsoNormal">><i> source/common/primitives.cpp | 2 +<o:p></o:p></i></p>
<p class="MsoNormal">><i> 7 files changed, 1063 insertions(+), 750 deletions(-)<o:p></o:p></i></p>
<p class="MsoNormal">><i> create mode 100644 source/common/aarch64/ssd-a-sve.S<o:p></o:p></i></p>
<p class="MsoNormal">><i> delete mode 100644 source/common/aarch64/ssd-a-sve2.S<o:p></o:p></i></p>
<p class="MsoNormal">><i><o:p> </o:p></i></p>
<p class="MsoNormal">><i>-- <o:p></o:p></i></p>
<p class="MsoNormal">><i>2.39.5 (Apple Git-154)<o:p></o:p></i></p>
<p class="MsoNormal">><i><o:p> </o:p></i></p>
<p class="MsoNormal">><i>_______________________________________________<o:p></o:p></i></p>
<p class="MsoNormal">><i>x265-devel mailing list<o:p></o:p></i></p>
<p class="MsoNormal">><i><a href="https://mailman.videolan.org/listinfo/x265-devel">x265-devel at videolan.org</a><o:p></o:p></i></p>
<p class="MsoNormal">><i><a href="https://mailman.videolan.org/listinfo/x265-devel">https://mailman.videolan.org/listinfo/x265-devel</a></i></p>
<p class="MsoNormal"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US"><o:p> </o:p></span></p>
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