<div data-ntes="ntes_mail_body_root" style="line-height:1.7;color:#000000;font-size:14px;font-family:Arial"><div id="spnEditorContent"><p style="margin: 0;">Hi Changsheng,</p><p style="margin: 0;"><br></p><p style="margin: 0;">Thank you for providing so much detailed information. I am glad to see that RISC-VV is gradually maturing.</p><p style="margin: 0;"><br></p><p style="margin: 0;">I conducted a simple experiment on GCC, it can automatically generate vectorized code now. However, I found a special instruction vlseg4e32.v in output, and consulted the RISC-VV documentation. I got many doubts.</p><p style="margin: 0;">Such as registers is (V8, V9, V10, V11) in document, or (V8, V10, V12, V14) in GCC.</p><p style="margin: 0;">And, there are still many ASM instruction's details that only exist in fragmented PPT from different user/companies, without a unified official document</p><p style="margin: 0;"><br></p><p style="margin: 0;"></p><p style="margin: 0;">These issues may lead to repeated code rework in the future, which makes me still not recommend accepting RISC-VV now.</p><p style="margin: 0;">If possible, please help the RISC-V community to improving the RISC-VV ISA documentation. I am pleased to accept RISC-VV as one of the target platforms in the future.</p><p style="margin: 0;"><br></p><p style="margin: 0;">Regards,<br>Chen</p></div><div style="position:relative;zoom:1"></div><div id="divNeteaseMailCard"></div><p style="margin: 0;"><br></p><p style="margin: 0;">Code</p><div style="background-color: rgb(255, 255, 254); font-family: Consolas, "Liberation Mono", Courier, monospace, Consolas, "Courier New", monospace; line-height: 19px; white-space: pre;"><div><span style="color: #0000ff;">int</span> test1(<span style="color: #0000ff;">int</span> *x, <span style="color: #0000ff;">int</span> N)</div><div>{</div><div> <span style="color: #0000ff;">int</span> sum = <span style="color: #098658;">0</span>;</div><div> <span style="color: #0000ff;">if</span> (__builtin_expect(N % <span style="color: #098658;">4</span>, <span style="color: #098658;">0</span>))</div><div> {</div><div> <span style="color: #0000ff;">for</span>(<span style="color: #0000ff;">int</span> i = <span style="color: #098658;">0</span>; i < N; i+=<span style="color: #098658;">4</span>)</div><div> {</div><div> sum += (x[i+<span style="color: #098658;">0</span>] + x[i+<span style="color: #098658;">1</span>] + x[i+<span style="color: #098658;">2</span>] + x[i+<span style="color: #098658;">3</span>]);</div><div> }</div><div> }</div><div> <span style="color: #0000ff;">else</span></div><div> __builtin_unreachable();</div><div> <span style="color: #0000ff;">return</span> sum;</div><div>}</div></div><p style="margin: 0;"><br></p><p style="margin: 0;">GCC output</p><div style="background-color: rgb(255, 255, 254); font-family: Consolas, "Liberation Mono", Courier, monospace, Consolas, "Courier New", monospace; line-height: 19px; white-space: pre;"><div><span style="color: #0000ff;">test1</span>(<span style="color: #008080;">int</span>*, <span style="color: #008080;">int</span>):</div><div> <span style="color: #0000ff;">ble</span> <span style="color: #008080;">a1</span>,<span style="color: #008080;">zero</span>,<span style="color: #008080;">.L4</span></div><div> <span style="color: #0000ff;">vsetvli</span> <span style="color: #008080;">a5</span>,<span style="color: #008080;">zero</span>,<span style="color: #008080;">e32</span>,<span style="color: #008080;">m2</span>,<span style="color: #008080;">ta</span>,<span style="color: #008080;">ma</span></div><div> <span style="color: #0000ff;">addiw</span> <span style="color: #008080;">a4</span>,<span style="color: #008080;">a1</span>,-<span style="color: #098658;">1</span></div><div> <span style="color: #0000ff;">vmv.v.i</span> <span style="color: #008080;">v4</span>,<span style="color: #098658;">0</span></div><div> <span style="color: #0000ff;">srliw</span> <span style="color: #008080;">a4</span>,<span style="color: #008080;">a4</span>,<span style="color: #098658;">2</span></div><div> <span style="color: #0000ff;">addiw</span> <span style="color: #008080;">a4</span>,<span style="color: #008080;">a4</span>,<span style="color: #098658;">1</span></div><div><span style="color: #0000ff;">.L3</span>:</div><div> <span style="color: #0000ff;">vsetvli</span> <span style="color: #008080;">a5</span>,<span style="color: #008080;">a4</span>,<span style="color: #008080;">e32</span>,<span style="color: #008080;">m2</span>,<span style="color: #008080;">tu</span>,<span style="color: #008080;">ma</span></div><div> <span style="color: #0000ff;"><b>vlseg4e32.v</b></span> <span style="color: #008080;">v8</span>,(<span style="color: #008080;">a0</span>)</div><div> <span style="color: #0000ff;">slli</span> <span style="color: #008080;">a3</span>,<span style="color: #008080;">a5</span>,<span style="color: #098658;">4</span></div><div> <span style="color: #0000ff;">sub</span> <span style="color: #008080;">a4</span>,<span style="color: #008080;">a4</span>,<span style="color: #008080;">a5</span></div><div> <span style="color: #0000ff;">add</span> <span style="color: #008080;">a0</span>,<span style="color: #008080;">a0</span>,<span style="color: #008080;">a3</span></div><div> <span style="color: #0000ff;">vadd.vv</span> <span style="color: #008080;">v2</span>,<span style="color: #008080;">v10</span>,<span style="color: #008080;">v8</span></div><div> <span style="color: #0000ff;">vadd.vv</span> <span style="color: #008080;">v2</span>,<span style="color: #008080;">v2</span>,<span style="color: #008080;">v12</span></div><div> <span style="color: #0000ff;">vadd.vv</span> <span style="color: #008080;">v2</span>,<span style="color: #008080;">v2</span>,<span style="color: #008080;">v14</span></div><div> <span style="color: #0000ff;">vadd.vv</span> <span style="color: #008080;">v4</span>,<span style="color: #008080;">v4</span>,<span style="color: #008080;">v2</span></div><div> <span style="color: #0000ff;">bne</span> <span style="color: #008080;">a4</span>,<span style="color: #008080;">zero</span>,<span style="color: #008080;">.L3</span></div><div> <span style="color: #0000ff;">vsetvli</span> <span style="color: #008080;">a5</span>,<span style="color: #008080;">zero</span>,<span style="color: #008080;">e32</span>,<span style="color: #008080;">m2</span>,<span style="color: #008080;">ta</span>,<span style="color: #008080;">ma</span></div><div> <span style="color: #0000ff;">vmv.s.x</span> <span style="color: #008080;">v1</span>,<span style="color: #008080;">zero</span></div><div> <span style="color: #0000ff;">vredsum.vs</span> <span style="color: #008080;">v4</span>,<span style="color: #008080;">v4</span>,<span style="color: #008080;">v1</span></div><div> <span style="color: #0000ff;">vmv.x.s</span> <span style="color: #008080;">a0</span>,<span style="color: #008080;">v4</span></div><div> <span style="color: #0000ff;">ret</span></div><div><span style="color: #0000ff;">.L4</span>:</div><div> <span style="color: #0000ff;">li</span> <span style="color: #008080;">a0</span>,<span style="color: #098658;">0</span></div><div> <span style="color: #0000ff;">ret</span></div></div><p style="margin: 0;"><br></p><div style="margin: 0;">RISC-V Document</div><div style="margin: 0;"><div class="markdown-heading" dir="auto" style="box-sizing: border-box; position: relative; color: rgb(31, 35, 40); font-family: -apple-system, BlinkMacSystemFont, "Segoe UI", "Noto Sans", Helvetica, Arial, sans-serif, "Apple Color Emoji", "Segoe UI Emoji"; font-size: 16px;"><h4 id="user-content-vector-strided-segment-loads-and-stores" tabindex="-1" class="heading-element" dir="auto" style="box-sizing: border-box; margin-top: 24px; margin-bottom: 16px; font-size: 1em; line-height: 1.25;">7.8.2. Vector Strided Segment Loads and Stores</h4><a id="user-content-782-vector-strided-segment-loads-and-stores" class="anchor" aria-label="Permalink: 7.8.2. Vector Strided Segment Loads and Stores" href="https://github.com/riscvarchive/riscv-v-spec/blob/v1.0/v-spec.adoc#782-vector-strided-segment-loads-and-stores" style="box-sizing: border-box; background-color: rgba(0, 0, 0, 0); color: rgb(9, 105, 218); float: left; padding-right: 4px; margin: auto; line-height: 1; position: absolute; top: 10px; left: -28px; display: flex; width: 28px; height: 28px; border-radius: 6px; opacity: 0; justify-content: center; align-items: center; transform: translateY(-50%); text-underline-offset: 0.2rem;"><svg class="octicon octicon-link" viewbox="0 0 16 16" version="1.1" width="16" height="16" aria-hidden="true"><path d="m7.775 3.275 1.25-1.25a3.5 3.5 0 1 1 4.95 4.95l-2.5 2.5a3.5 3.5 0 0 1-4.95 0 .751.751 0 0 1 .018-1.042.751.751 0 0 1 1.042-.018 1.998 1.998 0 0 0 2.83 0l2.5-2.5a2.002 2.002 0 0 0-2.83-2.83l-1.25 1.25a.751.751 0 0 1-1.042-.018.751.751 0 0 1-.018-1.042Zm-4.69 9.64a1.998 1.998 0 0 0 2.83 0l1.25-1.25a.751.751 0 0 1 1.042.018.751.751 0 0 1 .018 1.042l-1.25 1.25a3.5 3.5 0 1 1-4.95-4.95l2.5-2.5a3.5 3.5 0 0 1 4.95 0 .751.751 0 0 1-.018 1.042.751.751 0 0 1-1.042.018 1.998 1.998 0 0 0-2.83 0l-2.5 2.5a1.998 1.998 0 0 0 0 2.83Z"></path></svg></a></div><div dir="auto" style="box-sizing: border-box; color: rgb(31, 35, 40); font-family: -apple-system, BlinkMacSystemFont, "Segoe UI", "Noto Sans", Helvetica, Arial, sans-serif, "Apple Color Emoji", "Segoe UI Emoji"; font-size: 16px;"><p dir="auto" style="box-sizing: border-box; margin-top: 0px; margin-bottom: 16px;">Vector strided segment loads and stores move contiguous segments where each segment is separated by the byte-stride offset given in the <code style="box-sizing: border-box; font-family: ui-monospace, SFMono-Regular, "SF Mono", Menlo, Consolas, "Liberation Mono", monospace; font-size: 13.6px; padding: 0.2em 0.4em; margin: 0px; white-space-collapse: break-spaces; background-color: rgba(129, 139, 152, 0.12); border-radius: 6px;">rs2</code> GPR argument.</p></div><div dir="auto" style="box-sizing: border-box; color: rgb(31, 35, 40); font-family: -apple-system, BlinkMacSystemFont, "Segoe UI", "Noto Sans", Helvetica, Arial, sans-serif, "Apple Color Emoji", "Segoe UI Emoji"; font-size: 16px;"><markdown-accessiblity-table data-catalyst="" style="box-sizing: border-box; display: block;"><table style="border-spacing: 0px; border-collapse: collapse; margin-top: 0px; margin-bottom: 16px; display: block; width: max-content; max-width: 100%; overflow: auto; font-variant-numeric: tabular-nums;" id="ntes_editor_table_10010" class="ntes_not_fresh_table"><tbody style="box-sizing: border-box;"><tr style="box-sizing: border-box; border-top: 0.666667px solid rgba(209, 217, 224, 0.7);"><td style="box-sizing: border-box; padding: 6px 13px; border-color: rgb(209, 217, 224); border-style: solid; border-width: 0.666667px; border-image: none 100% / 1 / 0 stretch;"><div dir="auto" style="box-sizing: border-box; margin-bottom: 0px;">Note</div></td><td style="box-sizing: border-box; padding: 6px 13px; border-color: rgb(209, 217, 224); border-style: solid; border-width: 0.666667px; border-image: none 100% / 1 / 0 stretch;">Negative and zero strides are supported.</td></tr></tbody></table></markdown-accessiblity-table></div><div dir="auto" style="box-sizing: border-box; color: rgb(31, 35, 40); font-family: -apple-system, BlinkMacSystemFont, "Segoe UI", "Noto Sans", Helvetica, Arial, sans-serif, "Apple Color Emoji", "Segoe UI Emoji"; font-size: 16px;"><div dir="auto" style="box-sizing: border-box;"><pre style="box-sizing: border-box; font-family: ui-monospace, SFMono-Regular, "SF Mono", Menlo, Consolas, "Liberation Mono", monospace; font-size: 13.6px; margin-top: 0px; margin-bottom: 16px; overflow-wrap: normal; padding: 16px; overflow: auto; line-height: 1.45; background-color: rgb(246, 248, 250); border-radius: 6px;"> # Format
vlsseg<nf>e<eew>.v vd, (rs1), rs2, vm # Strided segment loads
vssseg<nf>e<eew>.v vs3, (rs1), rs2, vm # Strided segment stores
# Examples
vsetvli a1, t0, e8, ta, ma
vlsseg3e8.v v4, (x5), x6 # Load bytes at addresses x5+i*x6 into v4[i],
# and bytes at addresses x5+i*x6+1 into v5[i],
# and bytes at addresses x5+i*x6+2 into v6[i].
# Examples
vsetvli a1, t0, e32, ta, ma
vssseg2e32.v v2, (x5), x6 # Store words from v2[i] to address x5+i*x6
# and words from v3[i] to address x5+i*x6+4</pre></div></div></div><div style="margin: 0;"><br></div><p>At 2025-07-07 15:24:16, wu.changsheng@sanechips.com.cn wrote:</p><blockquote id="isReplyContent" style="PADDING-LEFT: 1ex; MARGIN: 0px 0px 0px 0.8ex; BORDER-LEFT: #ccc 1px solid"><div class="zcontentRow"><p>Hi Chen,</p><p><br></p><p>Thank you for your previous feedback.</p><p><br></p><p>I'd like to supplement some information about RISC-V Vector V1.0 and hope you can reconsider x265 support for the RISC-V architecture. </p><p><br></p><p>1. The RISC-V community considers Vector V1.0 a stable version. The RISC-V Vector V1.0 was officially approved and released in 2021. The server profile RVA23, released in October 2024, also specifies Vector V1.0, and The RISC-V Instruction Set Manual Volume published the same year adopts Vector V1.0 as well. </p><p>2. Many chip manufacturers already support RISC-V Vector Extension V1.0, such as the already released SiFive P670/P470, Andes NX27V, Alibaba C920, and SpaceMIT X100 CPUs. In the next year or two, many more vendors will launch chips supporting Vector V1.0.</p><p>3. GCC experimentally introduced RISC-V Vector support in GCC 12 (May 2022) and officially supported RISC-V Vector V1.0 in GCC 14 (May 2024).</p><p>4. The Linux kernel merged support for RISC-V Vector V1.0 in June 2023 and released it in the LTS 6.21 version. </p><p>5. Our company has already planned to deploy RISC-V servers in data centers, with x265 video encoding being one of the key business scenarios. We will continue contributing RISC-V architecture patches.</p><p style="font-size:14px;font-family:΢ÈíÑźÚ,Microsoft YaHei;"><br></p><p>RISC-V has garnered widespread attention and strong investment, leading to rapid development. I believe it will become another mainstream architecture following x86 and Arm. RISC-V is now commercially viable and deserves adoption by the x265 community.</p><p style="font-size:14px;font-family:΢ÈíÑźÚ,Microsoft YaHei;"><br></p><p style="font-size:14px;font-family:΢ÈíÑźÚ,Microsoft YaHei;"><br></p><div unonameen="Wu Changsheng0318004250" unonamech="Îâ²ýÊ¢0318004250" class="zMailSign"><div class="zMailSignContent"><p style="box-sizing: border-box; outline: 0px; white-space: normal; font-family: Arial, Helvetica, "Microsoft Yahei", sans-serif; margin-top: 0px; margin-bottom: 0px; padding: 0px; min-height: 14px; background-color: rgb(255, 255, 255); line-height: normal;">Best Wishes£¡</p><p style="box-sizing: border-box; outline: 0px; white-space: normal; font-family: Arial, Helvetica, "Microsoft Yahei", sans-serif; margin-top: 0px; margin-bottom: 0px; padding: 0px; min-height: 14px; background-color: rgb(255, 255, 255); line-height: normal;">Changsheng Wu</p><p style="box-sizing: border-box; outline: 0px; white-space: normal; font-family: Arial, Helvetica, "Microsoft Yahei", sans-serif; margin-top: 0px; margin-bottom: 0px; padding: 0px; min-height: 14px; background-color: rgb(255, 255, 255);"><span style="box-sizing: border-box; outline: 0px; line-height: normal;">M</span><span style="box-sizing: border-box; outline: 0px; font-family: arial, sans-serif, "Myriad Pro"; line-height: normal;">: +86 13776570034</span></p><p style="box-sizing: border-box; outline: 0px; white-space: normal; font-family: Arial, Helvetica, "Microsoft Yahei", sans-serif; margin-top: 0px; margin-bottom: 0px; padding: 0px; min-height: 14px; background-color: rgb(255, 255, 255);"><span style="box-sizing: border-box; outline: 0px; font-family: arial, sans-serif, "Myriad Pro"; line-height: normal;">E£ºwu.changsheng@sanechips.com.cn</span></p><p style="box-sizing: border-box; outline: 0px; white-space: normal; font-family: Arial, Helvetica, "Microsoft Yahei", sans-serif; margin-top: 0px; margin-bottom: 0px; padding: 0px; min-height: 14px; background-color: rgb(255, 255, 255); line-height: normal;">SANECHIPS TECHNOLOGY CO.,LTD.</p><p><br></p></div></div><div class="zhistoryRow" style="display:block"><div class="zhistoryDes" style="width: 100%; height: 28px; line-height: 28px; background-color: #E0E5E9; color: #1388FF; text-align: center;">Original</div><div id="zwriteHistoryContainer"><div class="control-group zhistoryPanel"><div class="zhistoryHeader" style="padding: 8px; background-color: #F5F6F8;"><div><strong>From: </strong><span class="zreadUserName">chen <chenm003@163.com></span></div><div><strong>To: </strong><span class="zreadUserName" style="display: inline;">Îâ²ýÊ¢0318004250;</span></div><div><strong>Cc: </strong><span class="zreadUserName" style="display: inline;">x265-devel@videolan.org <x265-devel@videolan.org>;</span><span class="zreadUserName" style="display: inline;">mahesh@multicorewareinc.com <mahesh@multicorewareinc.com>;</span><span class="zreadUserName" style="display: inline;">pavan.tarun@multicorewareinc.com <pavan.tarun@multicorewareinc.com>;</span><span class="zreadUserName" style="display: inline;">ÉòÏÔÀ´0318003851;</span><span class="zreadUserName" style="display: inline;">Ô¬¼Ñ0318004243;</span><span class="zreadUserName" style="display: inline;">Îâ²ýÊ¢0318004250;</span></div><div><strong>Date: </strong><span class="">2025Äê07ÔÂ07ÈÕ 03:28</span></div><div><strong>Subject: </strong><span class="zreadTitle"><strong>Re:[x265] [PATCH] RISCV64: add copy_cnt assembly optimization</strong></span></div></div><div class="zhistoryContent"><div style="line-height:1.7;color:#000000;font-size:14px;font-family:Arial" data-ntes="ntes_mail_body_root"><div id="spnEditorContent"><p style="margin: 0;">Hi Changsheng,</p><p style="margin: 0;"><br></p><p style="margin: 0;">Thank for the patches.</p><p style="margin: 0;"><br></p><p style="margin: 0;">However, I don't think RISC-V Extension-V stable enough nowadays.</p><p style="margin: 0px;">v1.0 frozen at September 2021</p><p style="margin: 0px;">v1.1 public review at May 2023</p><div>no more update until July 2025</div><br><p style="margin: 0px;">And most instructions has not behavior description,</p><p style="margin: 0px;"><br></p><p style="margin: 0px;">For example, <strong>vredsum.vs</strong> in the patch</p><p style="margin: 0px;">vredsum.vs vd, vs2, vs1, vm # vd[0] = sum( vs1[0] , vs2[*] )</p><p style="margin: 0px;"><br></p><p style="margin: 0px;">I just guess it is<br>vd[0] = vs1[0] + sum(vs2[*])</p><p style="margin: 0px;"><br></p><p style="margin: 0px;">Another example is <strong>vlse8.v</strong>,</p><p style="margin: 0px;">I may guess it is equal to x86 PSHUFB or ARM VTBL,</p><p style="margin: 0px;"><br></p><p style="margin: 0px;">Above example I just guess, I can't confirm my concept in past couple years, too many similar problem inside RISC-V Extension-V</p><p style="margin: 0px;">So, I suggest do not integrate / implement RISC-V patch, until specification become stable enough.</p><p style="margin: 0;"><br></p><p style="margin: 0;">Rgards,</p></div><div style="margin: 0;">Chen</div><p>2025-07-06 10:08:25£¬wu.changsheng@sanechips.com.cn </p><blockquote style="PADDING-LEFT: 1ex; MARGIN: 0px 0px 0px 0.8ex; BORDER-LEFT: #ccc 1px solid" id="isReplyContent"><div class=""><p style="font-size:14px;font-family:΢ÈíÑźÚ,Microsoft YaHei;"><span style="font-family: sans-serif;">From 7562e3a834a6a5ea76ab1b97acf915e095646cd5 Mon Sep 17 00:00:00 2001</span><br></p><p>From: Changsheng Wu <wu.changsheng@sanechips.com.cn></p><p>Date: Sat, 5 Jul 2025 23:09:14 +0800</p><p>Subject: [PATCH] RISCV64: add copy_cnt assembly optimization</p><p><br></p><p>TestBench test result:</p><p> copy_cnt[4x4] | 1.34x | 123.12 | 165.06</p><p> copy_cnt[8x8] | 2.64x | 214.07 | 564.26</p><p>copy_cnt[16x16] | 3.96x | 563.83 | 2232.00</p><p>copy_cnt[32x32] | 7.44x | 2144.80 | 15954.42</p><p><br></p></div></blockquote></div></div></div></div></div><p><br></p></div></blockquote><br></div>