[x264-devel] [PATCH 2/2] MIPS MSA Common Macros
Rishikesh More
Rishikesh.More at imgtec.com
Thu Jun 18 14:15:16 CEST 2015
Please ignore/ discard this patch. We will send new code in subsequent patches.
Regards,
Rishikesh
-----Original Message-----
From: Rishikesh More
Sent: Wednesday, June 10, 2015 7:23 PM
To: x264-devel at videolan.org
Cc: Rishikesh More
Subject: [PATCH 2/2] MIPS MSA Common Macros
From: Rishikesh More <rishikesh.more at imgtec.com>
This patch includes restructuring of existing macros and addition of more generic macros.
This change was necessary to avoid repeated review comments in remaining patches which we were about to submit.
Also this patch reduces number of code lines due to maximum use of generic macros, allows better code alignment & readability.
Overall, this patch set is just upgrading the code with styling changes and will bring it in sync with MIPS-SIMD optimized latest codebase at our end.
Signed-off-by: Rishikesh More <rishikesh.more at imgtec.com>
---
common/mips/macros.h | 1830 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 1830 insertions(+)
create mode 100644 common/mips/macros.h
diff --git a/common/mips/macros.h b/common/mips/macros.h
new file mode 100644
index 0000000..4af5ec6
--- /dev/null
+++ b/common/mips/macros.h
@@ -0,0 +1,1830 @@
+/*****************************************************************************
+ * macros.h: mips msa macros
+ *****************************************************************************
+ * Copyright (C) 2009-2015 x264 project
+ *
+ * Authors: Parag Salasakar <parag.salasakar at imgtec.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02111, USA.
+ *
+ * This program is also available under a commercial proprietary license.
+ * For more information, contact us at licensing at x264.com.
+ *****************************************************************************/
+
+#ifndef X264_MIPS_MACROS_H
+#define X264_MIPS_MACROS_H
+
+#include <stdint.h>
+#include <msa.h>
+
+#define LD_B( RTYPE, p_src ) *( ( RTYPE * )( p_src ) )
+#define LD_UB( ... ) LD_B( v16u8, __VA_ARGS__ )
+#define LD_SB( ... ) LD_B( v16i8, __VA_ARGS__ )
+
+#define LD_H( RTYPE, p_src ) *( ( RTYPE * )( p_src ) )
+#define LD_SH( ... ) LD_H( v8i16, __VA_ARGS__ )
+
+#define LD_W( RTYPE, p_src ) *( ( RTYPE * )( p_src ) )
+#define LD_SW( ... ) LD_W( v4i32, __VA_ARGS__ )
+
+#define ST_B( RTYPE, in, p_dst ) *( ( RTYPE * )( p_dst ) ) = ( in )
+#define ST_UB( ... ) ST_B( v16u8, __VA_ARGS__ )
+#define ST_SB( ... ) ST_B( v16i8, __VA_ARGS__ )
+
+#define ST_H( RTYPE, in, p_dst ) *( ( RTYPE * )( p_dst ) ) = ( in )
+#define ST_UH( ... ) ST_H( v8u16, __VA_ARGS__ )
+#define ST_SH( ... ) ST_H( v8i16, __VA_ARGS__ )
+
+#if ( __mips_isa_rev >= 6 )
+ #define LH( p_src ) \
+ ( { \
+ uint8_t *p_src_m = ( uint8_t * ) ( p_src ); \
+ uint16_t u_val_h_m; \
+ \
+ asm volatile ( \
+ "lh %[u_val_h_m], %[p_src_m] \n\t" \
+ \
+ : [u_val_h_m] "=r" ( u_val_h_m ) \
+ : [p_src_m] "m" ( *p_src_m ) \
+ ); \
+ \
+ u_val_h_m; \
+ } )
+
+ #define LW( p_src ) \
+ ( { \
+ uint8_t *p_src_m = ( uint8_t * ) ( p_src ); \
+ uint32_t u_val_w_m; \
+ \
+ asm volatile ( \
+ "lw %[u_val_w_m], %[p_src_m] \n\t" \
+ \
+ : [u_val_w_m] "=r" ( u_val_w_m ) \
+ : [p_src_m] "m" ( *p_src_m ) \
+ ); \
+ \
+ u_val_w_m; \
+ } )
+
+ #if ( __mips == 64 )
+ #define LD( p_src ) \
+ ( { \
+ uint8_t *p_src_m = ( uint8_t * ) ( p_src ); \
+ uint64_t u_val_d_m = 0; \
+ \
+ asm volatile ( \
+ "ld %[u_val_d_m], %[p_src_m] \n\t" \
+ \
+ : [u_val_d_m] "=r" ( u_val_d_m ) \
+ : [p_src_m] "m" ( *p_src_m ) \
+ ); \
+ \
+ u_val_d_m; \
+ } )
+ #else // !( __mips == 64 )
+ #define LD( p_src ) \
+ ( { \
+ uint8_t *p_src_m = ( uint8_t * ) ( p_src ); \
+ uint32_t u_val0_m, u_val1_m; \
+ uint64_t u_val_d_m = 0; \
+ \
+ u_val0_m = LW( p_src_m ); \
+ u_val1_m = LW( p_src_m + 4 ); \
+ \
+ u_val_d_m = ( uint64_t ) ( u_val1_m ); \
+ u_val_d_m = ( uint64_t ) ( ( u_val_d_m << 32 ) & \
+ 0xFFFFFFFF00000000 ); \
+ u_val_d_m = ( uint64_t ) ( u_val_d_m | ( uint64_t ) u_val0_m ); \
+ \
+ u_val_d_m; \
+ } )
+ #endif // ( __mips == 64 )
+
+ #define SH( u_val, p_dst ) \
+ { \
+ uint8_t *p_dst_m = ( uint8_t * ) ( p_dst ); \
+ uint16_t u_val_h_m = ( u_val ); \
+ \
+ asm volatile ( \
+ "sh %[u_val_h_m], %[p_dst_m] \n\t" \
+ \
+ : [p_dst_m] "=m" ( *p_dst_m ) \
+ : [u_val_h_m] "r" ( u_val_h_m ) \
+ ); \
+ }
+
+ #define SW( u_val, p_dst ) \
+ { \
+ uint8_t *p_dst_m = ( uint8_t * ) ( p_dst ); \
+ uint32_t u_val_w_m = ( u_val ); \
+ \
+ asm volatile ( \
+ "sw %[u_val_w_m], %[p_dst_m] \n\t" \
+ \
+ : [p_dst_m] "=m" ( *p_dst_m ) \
+ : [u_val_w_m] "r" ( u_val_w_m ) \
+ ); \
+ }
+
+ #define SD( u_val, p_dst ) \
+ { \
+ uint8_t *p_dst_m = ( uint8_t * ) ( p_dst ); \
+ uint64_t u_val_d_m = ( u_val ); \
+ \
+ asm volatile ( \
+ "sd %[u_val_d_m], %[p_dst_m] \n\t" \
+ \
+ : [p_dst_m] "=m" ( *p_dst_m ) \
+ : [u_val_d_m] "r" ( u_val_d_m ) \
+ ); \
+ }
+
+#else // !( __mips_isa_rev >= 6 )
+ #define LH( p_src ) \
+ ( { \
+ uint8_t *p_src_m = ( uint8_t * ) ( p_src ); \
+ uint16_t u_val_h_m; \
+ \
+ asm volatile ( \
+ "ulh %[u_val_h_m], %[p_src_m] \n\t" \
+ \
+ : [u_val_h_m] "=r" ( u_val_h_m ) \
+ : [p_src_m] "m" ( *p_src_m ) \
+ ); \
+ \
+ u_val_h_m; \
+ } )
+
+ #define LW( p_src ) \
+ ( { \
+ uint8_t *p_src_m = ( uint8_t * ) ( p_src ); \
+ uint32_t u_val_w_m; \
+ \
+ asm volatile ( \
+ "ulw %[u_val_w_m], %[p_src_m] \n\t" \
+ \
+ : [u_val_w_m] "=r" ( u_val_w_m ) \
+ : [p_src_m] "m" ( *p_src_m ) \
+ ); \
+ \
+ u_val_w_m; \
+ } )
+
+ #if ( __mips == 64 )
+ #define LD( p_src ) \
+ ( { \
+ uint8_t *p_src_m = ( uint8_t * ) ( p_src ); \
+ uint64_t u_val_d_m = 0; \
+ \
+ asm volatile ( \
+ "uld %[u_val_d_m], %[p_src_m] \n\t" \
+ \
+ : [u_val_d_m] "=r" ( u_val_d_m ) \
+ : [p_src_m] "m" ( *p_src_m ) \
+ ); \
+ \
+ u_val_d_m; \
+ } )
+ #else // !( __mips == 64 )
+ #define LD( p_src ) \
+ ( { \
+ uint8_t *psrc_m1 = ( uint8_t * ) ( p_src ); \
+ uint32_t u_val0_m, u_val1_m; \
+ uint64_t u_val_d_m = 0; \
+ \
+ u_val0_m = LW( psrc_m1 ); \
+ u_val1_m = LW( psrc_m1 + 4 ); \
+ \
+ u_val_d_m = ( uint64_t ) ( u_val1_m ); \
+ u_val_d_m = ( uint64_t ) ( ( u_val_d_m << 32 ) & \
+ 0xFFFFFFFF00000000 ); \
+ u_val_d_m = ( uint64_t ) ( u_val_d_m | ( uint64_t ) u_val0_m ); \
+ \
+ u_val_d_m; \
+ } )
+ #endif // ( __mips == 64 )
+
+ #define SH( u_val, p_dst ) \
+ { \
+ uint8_t *p_dst_m = ( uint8_t * ) ( p_dst ); \
+ uint16_t u_val_h_m = ( u_val ); \
+ \
+ asm volatile ( \
+ "ush %[u_val_h_m], %[p_dst_m] \n\t" \
+ \
+ : [p_dst_m] "=m" ( *p_dst_m ) \
+ : [u_val_h_m] "r" ( u_val_h_m ) \
+ ); \
+ }
+
+ #define SW( u_val, p_dst ) \
+ { \
+ uint8_t *p_dst_m = ( uint8_t * ) ( p_dst ); \
+ uint32_t u_val_w_m = ( u_val ); \
+ \
+ asm volatile ( \
+ "usw %[u_val_w_m], %[p_dst_m] \n\t" \
+ \
+ : [p_dst_m] "=m" ( *p_dst_m ) \
+ : [u_val_w_m] "r" ( u_val_w_m ) \
+ ); \
+ }
+
+ #define SD( u_val, p_dst ) \
+ { \
+ uint8_t *p_dst_m1 = ( uint8_t * ) ( p_dst ); \
+ uint32_t u_val0_m, u_val1_m; \
+ \
+ u_val0_m = ( uint32_t ) ( ( u_val ) & 0x00000000FFFFFFFF ); \
+ u_val1_m = ( uint32_t ) ( ( ( u_val ) >> 32 ) & 0x00000000FFFFFFFF ); \
+ \
+ SW( u_val0_m, p_dst_m1 ); \
+ SW( u_val1_m, p_dst_m1 + 4 ); \
+ }
+
+#endif // ( __mips_isa_rev >= 6 )
+
+/* Description : Load 4 words with stride
+ Arguments : Inputs - p_src ( source pointer to load from )
+ - stride
+ Outputs - out0, out1, out2, out3
+ Details : Loads word in 'out0' from ( p_src )
+ Loads word in 'out1' from ( p_src + stride )
+ Loads word in 'out2' from ( p_src + 2 * stride )
+ Loads word in 'out3' from ( p_src + 3 * stride )
+*/
+#define LW4( p_src, stride, out0, out1, out2, out3 ) \
+{ \
+ out0 = LW( ( p_src ) ); \
+ out1 = LW( ( p_src ) + stride ); \
+ out2 = LW( ( p_src ) + 2 * stride ); \
+ out3 = LW( ( p_src ) + 3 * stride ); \
+}
+
+/* Description : Store 4 words with stride
+ Arguments : Inputs - in0, in1, in2, in3, p_dst, stride
+ Details : Stores word from 'in0' to ( p_dst )
+ Stores word from 'in1' to ( p_dst + stride )
+ Stores word from 'in2' to ( p_dst + 2 * stride )
+ Stores word from 'in3' to ( p_dst + 3 * stride )
+*/
+#define SW4( in0, in1, in2, in3, p_dst, stride ) \
+{ \
+ SW( in0, ( p_dst ) ) \
+ SW( in1, ( p_dst ) + stride ); \
+ SW( in2, ( p_dst ) + 2 * stride ); \
+ SW( in3, ( p_dst ) + 3 * stride ); \
+}
+
+/* Description : Store 4 double words with stride
+ Arguments : Inputs - in0, in1, in2, in3, p_dst, stride
+ Details : Stores double word from 'in0' to ( p_dst )
+ Stores double word from 'in1' to ( p_dst + stride )
+ Stores double word from 'in2' to ( p_dst + 2 * stride )
+ Stores double word from 'in3' to ( p_dst + 3 * stride )
+*/
+#define SD4( in0, in1, in2, in3, p_dst, stride ) \
+{ \
+ SD( in0, ( p_dst ) ) \
+ SD( in1, ( p_dst ) + stride ); \
+ SD( in2, ( p_dst ) + 2 * stride ); \
+ SD( in3, ( p_dst ) + 3 * stride ); \
+}
+
+/* Description : Load vectors with 16 byte elements with stride
+ Arguments : Inputs - p_src ( source pointer to load from )
+ - stride
+ Outputs - out0, out1
+ Return Type - as per RTYPE
+ Details : Loads 16 byte elements in 'out0' from ( p_src )
+ Loads 16 byte elements in 'out1' from ( p_src + stride )
+*/
+#define LD_B2( RTYPE, p_src, stride, out0, out1 ) \
+{ \
+ out0 = LD_B( RTYPE, ( p_src ) ); \
+ out1 = LD_B( RTYPE, ( p_src ) + stride ); \
+}
+#define LD_UB2( ... ) LD_B2( v16u8, __VA_ARGS__ )
+#define LD_SB2( ... ) LD_B2( v16i8, __VA_ARGS__ )
+
+#define LD_B3( RTYPE, p_src, stride, out0, out1, out2 ) \
+{ \
+ LD_B2( RTYPE, ( p_src ), stride, out0, out1 ); \
+ out2 = LD_B( RTYPE, ( p_src ) + 2 * stride ); \
+}
+#define LD_UB3( ... ) LD_B3( v16u8, __VA_ARGS__ )
+#define LD_SB3( ... ) LD_B3( v16i8, __VA_ARGS__ )
+
+#define LD_B4( RTYPE, p_src, stride, out0, out1, out2, out3 ) \
+{ \
+ LD_B2( RTYPE, ( p_src ), stride, out0, out1 ); \
+ LD_B2( RTYPE, ( p_src ) + 2 * stride , stride, out2, out3 ); \
+}
+#define LD_UB4( ... ) LD_B4( v16u8, __VA_ARGS__ )
+#define LD_SB4( ... ) LD_B4( v16i8, __VA_ARGS__ )
+
+#define LD_B5( RTYPE, p_src, stride, out0, out1, out2, out3, out4 ) \
+{ \
+ LD_B4( RTYPE, ( p_src ), stride, out0, out1, out2, out3 ); \
+ out4 = LD_B( RTYPE, ( p_src ) + 4 * stride ); \
+}
+#define LD_UB5( ... ) LD_B5( v16u8, __VA_ARGS__ )
+#define LD_SB5( ... ) LD_B5( v16i8, __VA_ARGS__ )
+
+#define LD_B8( RTYPE, p_src, stride, \
+ out0, out1, out2, out3, out4, out5, out6, out7 ) \
+{ \
+ LD_B4( RTYPE, ( p_src ), stride, out0, out1, out2, out3 ); \
+ LD_B4( RTYPE, ( p_src ) + 4 * stride, stride, out4, out5, out6, out7 ); \
+}
+#define LD_UB8( ... ) LD_B8( v16u8, __VA_ARGS__ )
+#define LD_SB8( ... ) LD_B8( v16i8, __VA_ARGS__ )
+
+/* Description : Load vectors with 8 halfword elements with stride
+ Arguments : Inputs - p_src ( source pointer to load from )
+ - stride
+ Outputs - out0, out1
+ Details : Loads 8 halfword elements in 'out0' from ( p_src )
+ Loads 8 halfword elements in 'out1' from ( p_src + stride )
+*/
+#define LD_H2( RTYPE, p_src, stride, out0, out1 ) \
+{ \
+ out0 = LD_H( RTYPE, ( p_src ) ); \
+ out1 = LD_H( RTYPE, ( p_src ) + ( stride ) ); \
+}
+#define LD_SH2( ... ) LD_H2( v8i16, __VA_ARGS__ )
+
+#define LD_H4( RTYPE, p_src, stride, out0, out1, out2, out3 ) \
+{ \
+ LD_H2( RTYPE, ( p_src ), stride, out0, out1 ); \
+ LD_H2( RTYPE, ( p_src ) + 2 * stride, stride, out2, out3 ); \
+}
+#define LD_SH4( ... ) LD_H4( v8i16, __VA_ARGS__ )
+
+#define LD_H8( RTYPE, p_src, stride, \
+ out0, out1, out2, out3, out4, out5, out6, out7 ) \
+{ \
+ LD_H4( RTYPE, ( p_src ), stride, out0, out1, out2, out3 ); \
+ LD_H4( RTYPE, ( p_src ) + 4 * stride, stride, out4, out5, out6, out7 ); \
+}
+#define LD_SH8( ... ) LD_H8( v8i16, __VA_ARGS__ )
+
+/* Description : Load as 4x4 block of signed halfword elements from 1D source
+ data into 4 vectors ( Each vector with 4 signed halfwords )
+ Arguments : Inputs - p_src
+ Outputs - out0, out1, out2, out3
+*/
+#define LD4x4_SH( p_src, out0, out1, out2, out3 ) \
+{ \
+ out0 = LD_SH( p_src ); \
+ out2 = LD_SH( p_src + 8 ); \
+ out1 = ( v8i16 ) __msa_ilvl_d( ( v2i64 ) out0, ( v2i64 ) out0 ); \
+ out3 = ( v8i16 ) __msa_ilvl_d( ( v2i64 ) out2, ( v2i64 ) out2 ); \
+}
+
+/* Description : Load 2 vectors of signed word elements with stride
+ Arguments : Inputs - p_src ( source pointer to load from )
+ - stride
+ Outputs - out0, out1
+ Return Type - signed word
+*/
+#define LD_SW2( p_src, stride, out0, out1 ) \
+{ \
+ out0 = LD_SW( ( p_src ) ); \
+ out1 = LD_SW( ( p_src ) + stride ); \
+}
+
+/* Description : Store vectors of 16 byte elements with stride
+ Arguments : Inputs - in0, in1, stride
+ Outputs - p_dst ( destination pointer to store to )
+ Details : Stores 16 byte elements from 'in0' to ( p_dst )
+ Stores 16 byte elements from 'in1' to ( p_dst + stride )
+*/
+#define ST_B2( RTYPE, in0, in1, p_dst, stride ) \
+{ \
+ ST_B( RTYPE, in0, ( p_dst ) ); \
+ ST_B( RTYPE, in1, ( p_dst ) + stride ); \
+}
+#define ST_UB2( ... ) ST_B2( v16u8, __VA_ARGS__ )
+
+#define ST_B4( RTYPE, in0, in1, in2, in3, p_dst, stride ) \
+{ \
+ ST_B2( RTYPE, in0, in1, ( p_dst ), stride ); \
+ ST_B2( RTYPE, in2, in3, ( p_dst ) + 2 * stride, stride ); \
+}
+#define ST_UB4( ... ) ST_B4( v16u8, __VA_ARGS__ )
+#define ST_SB4( ... ) ST_B4( v16i8, __VA_ARGS__ )
+
+#define ST_B8( RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
+ p_dst, stride ) \
+{ \
+ ST_B4( RTYPE, in0, in1, in2, in3, p_dst, stride ); \
+ ST_B4( RTYPE, in4, in5, in6, in7, ( p_dst ) + 4 * stride, stride ); \
+}
+#define ST_UB8( ... ) ST_B8( v16u8, __VA_ARGS__ )
+
+/* Description : Store vectors of 8 halfword elements with stride
+ Arguments : Inputs - in0, in1, stride
+ Outputs - p_dst ( destination pointer to store to )
+ Details : Stores 8 halfword elements from 'in0' to ( p_dst )
+ Stores 8 halfword elements from 'in1' to ( p_dst + stride )
+*/
+#define ST_H2( RTYPE, in0, in1, p_dst, stride ) \
+{ \
+ ST_H( RTYPE, in0, ( p_dst ) ); \
+ ST_H( RTYPE, in1, ( p_dst ) + stride ); \
+}
+#define ST_SH2( ... ) ST_H2( v8i16, __VA_ARGS__ )
+
+#define ST_H4( RTYPE, in0, in1, in2, in3, p_dst, stride ) \
+{ \
+ ST_H2( RTYPE, in0, in1, ( p_dst ), stride ); \
+ ST_H2( RTYPE, in2, in3, ( p_dst ) + 2 * stride, stride ); \
+}
+#define ST_SH4( ... ) ST_H4( v8i16, __VA_ARGS__ )
+
+#define ST_H8( RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, p_dst, stride ) \
+{ \
+ ST_H4( RTYPE, in0, in1, in2, in3, ( p_dst ), stride ); \
+ ST_H4( RTYPE, in4, in5, in6, in7, ( p_dst ) + 4 * stride, stride ); \
+}
+#define ST_SH8( ... ) ST_H8( v8i16, __VA_ARGS__ )
+
+/* Description : Store as 2x4 byte block to destination memory from input vector
+ Arguments : Inputs - in, stidx, p_dst, stride
+ Return Type - unsigned byte
+ Details : Index stidx halfword element from 'in' vector is copied and
+ stored on first line
+ Index stidx+1 halfword element from 'in' vector is copied and
+ stored on second line
+ Index stidx+2 halfword element from 'in' vector is copied and
+ stored on third line
+ Index stidx+3 halfword element from 'in' vector is copied and
+ stored on fourth line
+*/
+#define ST2x4_UB( in, stidx, p_dst, stride ) \
+{ \
+ uint16_t u_out0_m, u_out1_m, u_out2_m, u_out3_m; \
+ uint8_t *pblk_2x4_m = ( uint8_t * ) ( p_dst ); \
+ \
+ u_out0_m = __msa_copy_u_h( ( v8i16 ) in, ( stidx ) ); \
+ u_out1_m = __msa_copy_u_h( ( v8i16 ) in, ( stidx + 1 ) ); \
+ u_out2_m = __msa_copy_u_h( ( v8i16 ) in, ( stidx + 2 ) ); \
+ u_out3_m = __msa_copy_u_h( ( v8i16 ) in, ( stidx + 3 ) ); \
+ \
+ SH( u_out0_m, pblk_2x4_m ); \
+ SH( u_out1_m, pblk_2x4_m + stride ); \
+ SH( u_out2_m, pblk_2x4_m + 2 * stride ); \
+ SH( u_out3_m, pblk_2x4_m + 3 * stride ); \
+}
+
+/* Description : Store as 4x2 byte block to destination memory from input vector
+ Arguments : Inputs - in, pdst, stride
+ Return Type - unsigned byte
+ Details : Index 0 word element from input vector is copied and stored
+ on first line
+ Index 1 word element from input vector is copied and stored
+ on second line
+*/
+#define ST4x2_UB(in, pdst, stride) \
+{ \
+ uint32_t out0_m, out1_m; \
+ uint8_t *pblk_4x2_m = (uint8_t *) (pdst); \
+ \
+ out0_m = __msa_copy_u_w((v4i32) in, 0); \
+ out1_m = __msa_copy_u_w((v4i32) in, 1); \
+ \
+ SW(out0_m, pblk_4x2_m); \
+ SW(out1_m, pblk_4x2_m + stride); \
+}
+
+/* Description : Store as 4x4 byte block to destination memory from input vector
+ Arguments : Inputs - in0, in1, p_dst, stride
+ Return Type - unsigned byte
+ Details : Idx0 word element from input vector 'in0' is copied and stored
+ on first line
+ Idx1 word element from input vector 'in0' is copied and stored
+ on second line
+ Idx2 word element from input vector 'in1' is copied and stored
+ on third line
+ Idx3 word element from input vector 'in1' is copied and stored
+ on fourth line
+*/
+#define ST4x4_UB( in0, in1, idx0, idx1, idx2, idx3, p_dst, stride ) \
+{ \
+ uint32_t u_out0_m, u_out1_m, u_out2_m, u_out3_m; \
+ uint8_t *pblk_4x4_m = ( uint8_t * ) ( p_dst ); \
+ \
+ u_out0_m = __msa_copy_u_w( ( v4i32 ) in0, idx0 ); \
+ u_out1_m = __msa_copy_u_w( ( v4i32 ) in0, idx1 ); \
+ u_out2_m = __msa_copy_u_w( ( v4i32 ) in1, idx2 ); \
+ u_out3_m = __msa_copy_u_w( ( v4i32 ) in1, idx3 ); \
+ \
+ SW4( u_out0_m, u_out1_m, u_out2_m, u_out3_m, pblk_4x4_m, stride ); \
+}
+
+#define ST4x8_UB( in0, in1, p_dst, stride ) \
+{ \
+ uint8_t *pblk_4x8 = ( uint8_t * ) ( p_dst ); \
+ \
+ ST4x4_UB( in0, in0, 0, 1, 2, 3, pblk_4x8, stride ); \
+ ST4x4_UB( in1, in1, 0, 1, 2, 3, pblk_4x8 + 4 * stride, stride ); \
+}
+
+/* Description : Store as 8x1 byte block to destination memory from input vector
+ Arguments : Inputs - in, p_dst
+ Details : Index 0 double word element from input vector 'in' is copied
+ and stored to destination memory at ( p_dst )
+*/
+#define ST8x1_UB( in, p_dst ) \
+{ \
+ uint64_t u_out0_m; \
+ u_out0_m = __msa_copy_u_d( ( v2i64 ) in, 0 ); \
+ SD( u_out0_m, p_dst ); \
+}
+
+/* Description : Store as 8x4 byte block to destination memory from input
+ vectors
+ Arguments : Inputs - in0, in1, p_dst, stride
+ Details : Index 0 double word element from input vector 'in0' is copied
+ and stored to destination memory at ( pblk_8x4_m )
+ Index 1 double word element from input vector 'in0' is copied
+ and stored to destination memory at ( pblk_8x4_m + stride )
+ Index 0 double word element from input vector 'in1' is copied
+ and stored to destination memory at ( pblk_8x4_m + 2 * stride )
+ Index 1 double word element from input vector 'in1' is copied
+ and stored to destination memory at ( pblk_8x4_m + 3 * stride )
+*/
+#define ST8x4_UB( in0, in1, p_dst, stride ) \
+{ \
+ uint64_t u_out0_m, u_out1_m, u_out2_m, u_out3_m; \
+ uint8_t *pblk_8x4_m = ( uint8_t * ) ( p_dst ); \
+ \
+ u_out0_m = __msa_copy_u_d( ( v2i64 ) in0, 0 ); \
+ u_out1_m = __msa_copy_u_d( ( v2i64 ) in0, 1 ); \
+ u_out2_m = __msa_copy_u_d( ( v2i64 ) in1, 0 ); \
+ u_out3_m = __msa_copy_u_d( ( v2i64 ) in1, 1 ); \
+ \
+ SD4( u_out0_m, u_out1_m, u_out2_m, u_out3_m, pblk_8x4_m, stride ); \
+}
+
+/* Description : average with rounding ( in0 + in1 + 1 ) / 2.
+ Arguments : Inputs - in0, in1, in2, in3,
+ Outputs - out0, out1
+ Return Type - signed byte
+ Details : Each byte element from 'in0' vector is added with each byte
+ element from 'in1' vector. The addition of the elements plus 1
+ ( for rounding ) is done unsigned with full precision,
+ i.e. the result has one extra bit. Unsigned division by 2
+ ( or logical shift right by one bit ) is performed before writing
+ the result to vector 'out0'
+ Similar for the pair of 'in2' and 'in3'
+*/
+#define AVER_UB2( RTYPE, in0, in1, in2, in3, out0, out1 ) \
+{ \
+ out0 = ( RTYPE ) __msa_aver_u_b( ( v16u8 ) in0, ( v16u8 ) in1 ); \
+ out1 = ( RTYPE ) __msa_aver_u_b( ( v16u8 ) in2, ( v16u8 ) in3 ); \
+}
+#define AVER_UB2_UB( ... ) AVER_UB2( v16u8, __VA_ARGS__ )
+
+#define AVER_UB4( RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
+ out0, out1, out2, out3 ) \
+{ \
+ AVER_UB2( RTYPE, in0, in1, in2, in3, out0, out1 ) \
+ AVER_UB2( RTYPE, in4, in5, in6, in7, out2, out3 ) \
+}
+#define AVER_UB4_UB( ... ) AVER_UB4( v16u8, __VA_ARGS__ )
+
+/* Description : Immediate number of columns to slide with zero
+ Arguments : Inputs - in0, in1, slide_val
+ Outputs - out0, out1
+ Return Type - as per RTYPE
+ Details : Byte elements from 'zero_m' vector are slide into 'in0' by
+ number of elements specified by 'slide_val'
+*/
+#define SLDI_B2_0( RTYPE, in0, in1, out0, out1, slide_val ) \
+{ \
+ v16i8 zero_m = { 0 }; \
+ out0 = ( RTYPE ) __msa_sldi_b( ( v16i8 ) zero_m, \
+ ( v16i8 ) in0, slide_val ); \
+ out1 = ( RTYPE ) __msa_sldi_b( ( v16i8 ) zero_m, \
+ ( v16i8 ) in1, slide_val ); \
+}
+#define SLDI_B2_0_UB( ... ) SLDI_B2_0( v16u8, __VA_ARGS__ )
+
+/* Description : Immediate number of columns to slide
+ Arguments : Inputs - in0_0, in0_1, in1_0, in1_1, slide_val
+ Outputs - out0, out1
+ Return Type - as per RTYPE
+ Details : Byte elements from 'in0_0' vector are slide into 'in1_0' by
+ number of elements specified by 'slide_val'
+*/
+#define SLDI_B2( RTYPE, in0_0, in0_1, in1_0, in1_1, out0, out1, slide_val ) \
+{ \
+ out0 = ( RTYPE ) __msa_sldi_b( ( v16i8 ) in0_0, ( v16i8 ) in1_0, \
+ slide_val ); \
+ out1 = ( RTYPE ) __msa_sldi_b( ( v16i8 ) in0_1, ( v16i8 ) in1_1, \
+ slide_val ); \
+}
+#define SLDI_B2_UB( ... ) SLDI_B2( v16u8, __VA_ARGS__ )
+
+/* Description : Shuffle byte vector elements as per mask vector
+ Arguments : Inputs - in0, in1, in2, in3, mask0, mask1
+ Outputs - out0, out1
+ Return Type - as per RTYPE
+ Details : Selective byte elements from in0 & in1 are copied to out0 as
+ per control vector mask0
+ Selective byte elements from in2 & in3 are copied to out1 as
+ per control vector mask1
+*/
+#define VSHF_B2( RTYPE, in0, in1, in2, in3, mask0, mask1, out0, out1 ) \
+{ \
+ out0 = ( RTYPE ) __msa_vshf_b( ( v16i8 ) mask0, \
+ ( v16i8 ) in1, ( v16i8 ) in0 ); \
+ out1 = ( RTYPE ) __msa_vshf_b( ( v16i8 ) mask1, \
+ ( v16i8 ) in3, ( v16i8 ) in2 ); \
+}
+#define VSHF_B2_UB( ... ) VSHF_B2( v16u8, __VA_ARGS__ )
+#define VSHF_B2_SB( ... ) VSHF_B2( v16i8, __VA_ARGS__ )
+
+/* Description : Shuffle halfword vector elements as per mask vector
+ Arguments : Inputs - in0, in1, in2, in3, mask0, mask1
+ Outputs - out0, out1
+ Return Type - as per RTYPE
+ Details : Selective halfword elements from in0 & in1 are copied to out0
+ as per control vector mask0
+ Selective halfword elements from in2 & in3 are copied to out1
+ as per control vector mask1
+*/
+#define VSHF_H2( RTYPE, in0, in1, in2, in3, mask0, mask1, out0, out1 ) \
+{ \
+ out0 = ( RTYPE ) __msa_vshf_h( ( v8i16 ) mask0, \
+ ( v8i16 ) in1, ( v8i16 ) in0 ); \
+ out1 = ( RTYPE ) __msa_vshf_h( ( v8i16 ) mask1, \
+ ( v8i16 ) in3, ( v8i16 ) in2 ); \
+}
+#define VSHF_H2_SH( ... ) VSHF_H2( v8i16, __VA_ARGS__ )
+
+/* Description : Dot product of byte vector elements
+ Arguments : Inputs - mult0, mult1
+ cnst0, cnst1
+ Outputs - out0, out1
+ Return Type - unsigned halfword
+ Details : Unsigned byte elements from mult0 are multiplied with
+ unsigned byte elements from cnst0 producing a result
+ twice the size of input i.e. unsigned halfword.
+ Then this multiplication results of adjacent odd-even elements
+ are added together and stored to the out vector
+ ( 2 unsigned halfword results )
+*/
+#define DOTP_UB2( RTYPE, mult0, mult1, cnst0, cnst1, out0, out1 ) \
+{ \
+ out0 = ( RTYPE ) __msa_dotp_u_h( ( v16u8 ) mult0, ( v16u8 ) cnst0 ); \
+ out1 = ( RTYPE ) __msa_dotp_u_h( ( v16u8 ) mult1, ( v16u8 ) cnst1 ); \
+}
+#define DOTP_UB2_UH( ... ) DOTP_UB2( v8u16, __VA_ARGS__ )
+
+#define DOTP_UB4( RTYPE, mult0, mult1, mult2, mult3, \
+ cnst0, cnst1, cnst2, cnst3, \
+ out0, out1, out2, out3 ) \
+{ \
+ DOTP_UB2( RTYPE, mult0, mult1, cnst0, cnst1, out0, out1 ); \
+ DOTP_UB2( RTYPE, mult2, mult3, cnst2, cnst3, out2, out3 ); \
+}
+#define DOTP_UB4_UH( ... ) DOTP_UB4( v8u16, __VA_ARGS__ )
+
+/* Description : Dot product & addition of byte vector elements
+ Arguments : Inputs - mult0, mult1
+ cnst0, cnst1
+ Outputs - out0, out1
+ Return Type - signed halfword
+ Details : Signed byte elements from mult0 are multiplied with
+ signed byte elements from cnst0 producing a result
+ twice the size of input i.e. signed halfword.
+ Then this multiplication results of adjacent odd-even elements
+ are added to the out vector
+ ( 2 signed halfword results )
+*/
+#define DPADD_SB2( RTYPE, mult0, mult1, cnst0, cnst1, out0, out1 ) \
+{ \
+ out0 = ( RTYPE ) __msa_dpadd_s_h( ( v8i16 ) out0, \
+ ( v16i8 ) mult0, ( v16i8 ) cnst0 ); \
+ out1 = ( RTYPE ) __msa_dpadd_s_h( ( v8i16 ) out1, \
+ ( v16i8 ) mult1, ( v16i8 ) cnst1 ); \
+}
+#define DPADD_SB2_SH( ... ) DPADD_SB2( v8i16, __VA_ARGS__ )
+
+#define DPADD_SB4( RTYPE, mult0, mult1, mult2, mult3, \
+ cnst0, cnst1, cnst2, cnst3, out0, out1, out2, out3 ) \
+{ \
+ DPADD_SB2( RTYPE, mult0, mult1, cnst0, cnst1, out0, out1 ); \
+ DPADD_SB2( RTYPE, mult2, mult3, cnst2, cnst3, out2, out3 ); \
+}
+#define DPADD_SB4_SH( ... ) DPADD_SB4( v8i16, __VA_ARGS__ )
+
+/* Description : Dot product & addition of halfword vector elements
+ Arguments : Inputs - mult0, mult1
+ cnst0, cnst1
+ Outputs - out0, out1
+ Return Type - signed word
+ Details : Signed halfword elements from mult0 are multiplied with
+ signed halfword elements from cnst0 producing a result
+ twice the size of input i.e. signed word.
+ Then this multiplication results of adjacent odd-even elements
+ are added to the out vector
+ ( 2 signed word results )
+*/
+#define DPADD_SH2( RTYPE, mult0, mult1, cnst0, cnst1, out0, out1 ) \
+{ \
+ out0 = ( RTYPE ) __msa_dpadd_s_w( ( v4i32 ) out0, \
+ ( v8i16 ) mult0, ( v8i16 ) cnst0 ); \
+ out1 = ( RTYPE ) __msa_dpadd_s_w( ( v4i32 ) out1, \
+ ( v8i16 ) mult1, ( v8i16 ) cnst1 ); \
+}
+#define DPADD_SH2_SW( ... ) DPADD_SH2( v4i32, __VA_ARGS__ )
+
+/* Description : Clips all halfword elements of input vector between min & max
+ out = ( ( in ) < ( min ) ) ? ( min ) : ( ( ( in ) > ( max ) ) ? ( max ) : ( in ) )
+ Arguments : Inputs - in ( input vector )
+ - min ( min threshold )
+ - max ( max threshold )
+ Outputs - out_m ( output vector with clipped elements )
+ Return Type - signed halfword
+*/
+#define CLIP_SH( in, min, max ) \
+( { \
+ v8i16 out_m; \
+ \
+ out_m = __msa_max_s_h( ( v8i16 ) min, ( v8i16 ) in ); \
+ out_m = __msa_min_s_h( ( v8i16 ) max, ( v8i16 ) out_m ); \
+ out_m; \
+} )
+
+/* Description : Clips all signed halfword elements of input vector
+ between 0 & 255
+ Arguments : Inputs - in ( input vector )
+ Outputs - out_m ( output vector with clipped elements )
+ Return Type - signed halfword
+*/
+#define CLIP_SH_0_255( in ) \
+( { \
+ v8i16 max_m = __msa_ldi_h( 255 ); \
+ v8i16 out_m; \
+ \
+ out_m = __msa_maxi_s_h( ( v8i16 ) in, 0 ); \
+ out_m = __msa_min_s_h( ( v8i16 ) max_m, ( v8i16 ) out_m ); \
+ out_m; \
+} )
+#define CLIP_SH2_0_255( in0, in1 ) \
+{ \
+ in0 = CLIP_SH_0_255( in0 ); \
+ in1 = CLIP_SH_0_255( in1 ); \
+}
+#define CLIP_SH4_0_255( in0, in1, in2, in3 ) \
+{ \
+ CLIP_SH2_0_255( in0, in1 ); \
+ CLIP_SH2_0_255( in2, in3 ); \
+}
+
+/* Description : Addition of 4 signed word elements
+ 4 signed word elements of input vector are added together and
+ resulted integer sum is returned
+ Arguments : Inputs - in ( signed word vector )
+ Outputs - sum_m ( i32 sum )
+ Return Type - signed word
+*/
+#define HADD_SW_S32( in ) \
+( { \
+ v2i64 res0_m, res1_m; \
+ int32_t i_sum_m; \
+ \
+ res0_m = __msa_hadd_s_d( ( v4i32 ) in, ( v4i32 ) in ); \
+ res1_m = __msa_splati_d( res0_m, 1 ); \
+ res0_m = res0_m + res1_m; \
+ i_sum_m = __msa_copy_s_w( ( v4i32 ) res0_m, 0 ); \
+ i_sum_m; \
+} )
+
+/* Description : Addition of 8 unsigned halfword elements
+ 8 unsigned halfword elements of input vector are added
+ together and resulted integer sum is returned
+ Arguments : Inputs - in ( unsigned halfword vector )
+ Outputs - u_sum_m ( u32 sum )
+ Return Type - unsigned word
+*/
+#define HADD_UH_U32( in ) \
+( { \
+ v4u32 res_m; \
+ v2u64 res0_m, res1_m; \
+ uint32_t u_sum_m; \
+ \
+ res_m = __msa_hadd_u_w( ( v8u16 ) in, ( v8u16 ) in ); \
+ res0_m = __msa_hadd_u_d( res_m, res_m ); \
+ res1_m = ( v2u64 ) __msa_splati_d( ( v2i64 ) res0_m, 1 ); \
+ res0_m = res0_m + res1_m; \
+ u_sum_m = __msa_copy_u_w( ( v4i32 ) res0_m, 0 ); \
+ u_sum_m; \
+} )
+
+/* Description : Horizontal addition of signed byte vector elements
+ Arguments : Inputs - in0, in1
+ Outputs - out0, out1
+ Return Type - as per RTYPE
+ Details : Each signed odd byte element from 'in0' is added to
+ even signed byte element from 'in0' ( pairwise ) and the
+ halfword result is stored in 'out0'
+*/
+#define HADD_SB2( RTYPE, in0, in1, out0, out1 ) \
+{ \
+ out0 = ( RTYPE ) __msa_hadd_s_h( ( v16i8 ) in0, ( v16i8 ) in0 ); \
+ out1 = ( RTYPE ) __msa_hadd_s_h( ( v16i8 ) in1, ( v16i8 ) in1 ); \
+}
+#define HADD_SB4( RTYPE, in0, in1, in2, in3, out0, out1, out2, out3 ) \
+{ \
+ HADD_SB2( RTYPE, in0, in1, out0, out1 ); \
+ HADD_SB2( RTYPE, in2, in3, out2, out3 ); \
+}
+#define HADD_SB4_SH( ... ) HADD_SB4( v8i16, __VA_ARGS__ )
+
+/* Description : Horizontal addition of unsigned byte vector elements
+ Arguments : Inputs - in0, in1
+ Outputs - out0, out1
+ Return Type - as per RTYPE
+ Details : Each unsigned odd byte element from 'in0' is added to
+ even unsigned byte element from 'in0' ( pairwise ) and the
+ halfword result is stored in 'out0'
+*/
+#define HADD_UB2( RTYPE, in0, in1, out0, out1 ) \
+{ \
+ out0 = ( RTYPE ) __msa_hadd_u_h( ( v16u8 ) in0, ( v16u8 ) in0 ); \
+ out1 = ( RTYPE ) __msa_hadd_u_h( ( v16u8 ) in1, ( v16u8 ) in1 ); \
+}
+#define HADD_UB2_UH( ... ) HADD_UB2( v8u16, __VA_ARGS__ )
+
+#define HADD_UB4( RTYPE, in0, in1, in2, in3, out0, out1, out2, out3 ) \
+{ \
+ HADD_UB2( RTYPE, in0, in1, out0, out1 ); \
+ HADD_UB2( RTYPE, in2, in3, out2, out3 ); \
+}
+#define HADD_UB4_UH( ... ) HADD_UB4( v8u16, __VA_ARGS__ )
+
+/* Description : Horizontal subtraction of unsigned byte vector elements
+ Arguments : Inputs - in0, in1
+ Outputs - out0, out1
+ Return Type - as per RTYPE
+ Details : Each unsigned odd byte element from 'in0' is subtracted from
+ even unsigned byte element from 'in0' ( pairwise ) and the
+ halfword result is stored in 'out0'
+*/
+#define HSUB_UB2( RTYPE, in0, in1, out0, out1 ) \
+{ \
+ out0 = ( RTYPE ) __msa_hsub_u_h( ( v16u8 ) in0, ( v16u8 ) in0 ); \
+ out1 = ( RTYPE ) __msa_hsub_u_h( ( v16u8 ) in1, ( v16u8 ) in1 ); \
+}
+#define HSUB_UB2_SH( ... ) HSUB_UB2( v8i16, __VA_ARGS__ )
+
+#define HSUB_UB4( RTYPE, in0, in1, in2, in3, out0, out1, out2, out3 ) \
+{ \
+ HSUB_UB2( RTYPE, in0, in1, out0, out1 ); \
+ HSUB_UB2( RTYPE, in2, in3, out2, out3 ); \
+}
+#define HSUB_UB4_SH( ... ) HSUB_UB4( v8i16, __VA_ARGS__ )
+
+/* Description : SAD ( Sum of Absolute Difference )
+ Arguments : Inputs - in0, in1, ref0, ref1 ( unsigned byte src & ref )
+ Outputs - sad_m ( halfword vector with sad )
+ Return Type - unsigned halfword
+ Details : Absolute difference of all the byte elements from 'in0' with
+ 'ref0' is calculated and preserved in 'diff0'. From the 16
+ unsigned absolute diff values, even-odd pairs are added
+ together to generate 8 halfword results.
+*/
+#define SAD_UB2_UH( in0, in1, ref0, ref1 ) \
+( { \
+ v16u8 diff0_m, diff1_m; \
+ v8u16 sad_m = { 0 }; \
+ \
+ diff0_m = __msa_asub_u_b( ( v16u8 ) in0, ( v16u8 ) ref0 ); \
+ diff1_m = __msa_asub_u_b( ( v16u8 ) in1, ( v16u8 ) ref1 ); \
+ \
+ sad_m += __msa_hadd_u_h( ( v16u8 ) diff0_m, ( v16u8 ) diff0_m ); \
+ sad_m += __msa_hadd_u_h( ( v16u8 ) diff1_m, ( v16u8 ) diff1_m ); \
+ \
+ sad_m; \
+} )
+
+/* Description : Insert specified word elements from input vectors to 1
+ destination vector
+ Arguments : Inputs - in0, in1, in2, in3 ( 4 input vectors )
+ Outputs - out ( output vector )
+ Return Type - as per RTYPE
+*/
+#define INSERT_W2( RTYPE, in0, in1, out ) \
+{ \
+ out = ( RTYPE ) __msa_insert_w( ( v4i32 ) out, 0, in0 ); \
+ out = ( RTYPE ) __msa_insert_w( ( v4i32 ) out, 1, in1 ); \
+}
+#define INSERT_W2_SB( ... ) INSERT_W2( v16i8, __VA_ARGS__ )
+
+#define INSERT_W4( RTYPE, in0, in1, in2, in3, out ) \
+{ \
+ out = ( RTYPE ) __msa_insert_w( ( v4i32 ) out, 0, in0 ); \
+ out = ( RTYPE ) __msa_insert_w( ( v4i32 ) out, 1, in1 ); \
+ out = ( RTYPE ) __msa_insert_w( ( v4i32 ) out, 2, in2 ); \
+ out = ( RTYPE ) __msa_insert_w( ( v4i32 ) out, 3, in3 ); \
+}
+#define INSERT_W4_UB( ... ) INSERT_W4( v16u8, __VA_ARGS__ )
+#define INSERT_W4_SB( ... ) INSERT_W4( v16i8, __VA_ARGS__ )
+
+/* Description : Insert specified double word elements from input vectors to 1
+ destination vector
+ Arguments : Inputs - in0, in1 ( 2 input vectors )
+ Outputs - out ( output vector )
+ Return Type - as per RTYPE
+*/
+#define INSERT_D2( RTYPE, in0, in1, out ) \
+{ \
+ out = ( RTYPE ) __msa_insert_d( ( v2i64 ) out, 0, in0 ); \
+ out = ( RTYPE ) __msa_insert_d( ( v2i64 ) out, 1, in1 ); \
+}
+#define INSERT_D2_UB( ... ) INSERT_D2( v16u8, __VA_ARGS__ )
+
+/* Description : Interleave even halfword elements from vectors
+ Arguments : Inputs - in0, in1, in2, in3
+ Outputs - out0, out1
+ Return Type - as per RTYPE
+ Details : Even halfword elements of 'in0' and even halfword
+ elements of 'in1' are interleaved and copied to 'out0'
+ Even halfword elements of 'in2' and even halfword
+ elements of 'in3' are interleaved and copied to 'out1'
+*/
+#define ILVEV_H2( RTYPE, in0, in1, in2, in3, out0, out1 ) \
+{ \
+ out0 = ( RTYPE ) __msa_ilvev_h( ( v8i16 ) in1, ( v8i16 ) in0 ); \
+ out1 = ( RTYPE ) __msa_ilvev_h( ( v8i16 ) in3, ( v8i16 ) in2 ); \
+}
+#define ILVEV_H2_UB( ... ) ILVEV_H2( v16u8, __VA_ARGS__ )
+
+/* Description : Interleave even double word elements from vectors
+ Arguments : Inputs - in0, in1, in2, in3
+ Outputs - out0, out1
+ Return Type - as per RTYPE
+ Details : Even double word elements of 'in0' and even double word
+ elements of 'in1' are interleaved and copied to 'out0'
+ Even double word elements of 'in2' and even double word
+ elements of 'in3' are interleaved and copied to 'out1'
+*/
+#define ILVEV_D2( RTYPE, in0, in1, in2, in3, out0, out1 ) \
+{ \
+ out0 = ( RTYPE ) __msa_ilvev_d( ( v2i64 ) in1, ( v2i64 ) in0 ); \
+ out1 = ( RTYPE ) __msa_ilvev_d( ( v2i64 ) in3, ( v2i64 ) in2 ); \
+}
+#define ILVEV_D2_UB( ... ) ILVEV_D2( v16u8, __VA_ARGS__ )
+
+/* Description : Interleave left half of byte elements from vectors
+ Arguments : Inputs - in0, in1, in2, in3
+ Outputs - out0, out1
+ Return Type - as per RTYPE
+ Details : Left half of byte elements of in0 and left half of byte
+ elements of in1 are interleaved and copied to out0.
+ Left half of byte elements of in2 and left half of byte
+ elements of in3 are interleaved and copied to out1.
+*/
+#define ILVL_B2( RTYPE, in0, in1, in2, in3, out0, out1 ) \
+{ \
+ out0 = ( RTYPE ) __msa_ilvl_b( ( v16i8 ) in0, ( v16i8 ) in1 ); \
+ out1 = ( RTYPE ) __msa_ilvl_b( ( v16i8 ) in2, ( v16i8 ) in3 ); \
+}
+#define ILVL_B2_UH( ... ) ILVL_B2( v8u16, __VA_ARGS__ )
+#define ILVL_B2_SH( ... ) ILVL_B2( v8i16, __VA_ARGS__ )
+
+#define ILVL_B4( RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
+ out0, out1, out2, out3 ) \
+{ \
+ ILVL_B2( RTYPE, in0, in1, in2, in3, out0, out1 ); \
+ ILVL_B2( RTYPE, in4, in5, in6, in7, out2, out3 ); \
+}
+#define ILVL_B4_UB( ... ) ILVL_B4( v16u8, __VA_ARGS__ )
+#define ILVL_B4_SB( ... ) ILVL_B4( v16i8, __VA_ARGS__ )
+#define ILVL_B4_UH( ... ) ILVL_B4( v8u16, __VA_ARGS__ )
+#define ILVL_B4_SH( ... ) ILVL_B4( v8i16, __VA_ARGS__ )
+
+/* Description : Interleave left half of halfword elements from vectors
+ Arguments : Inputs - in0, in1, in2, in3
+ Outputs - out0, out1
+ Return Type - as per RTYPE
+ Details : Left half of halfword elements of in0 and left half of halfword
+ elements of in1 are interleaved and copied to out0.
+ Left half of halfword elements of in2 and left half of halfword
+ elements of in3 are interleaved and copied to out1.
+*/
+#define ILVL_H2( RTYPE, in0, in1, in2, in3, out0, out1 ) \
+{ \
+ out0 = ( RTYPE ) __msa_ilvl_h( ( v8i16 ) in0, ( v8i16 ) in1 ); \
+ out1 = ( RTYPE ) __msa_ilvl_h( ( v8i16 ) in2, ( v8i16 ) in3 ); \
+}
+#define ILVL_H2_SH( ... ) ILVL_H2( v8i16, __VA_ARGS__ )
+#define ILVL_H2_SW( ... ) ILVL_H2( v4i32, __VA_ARGS__ )
+
+#define ILVL_H4( RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
+ out0, out1, out2, out3 ) \
+{ \
+ ILVL_H2( RTYPE, in0, in1, in2, in3, out0, out1 ); \
+ ILVL_H2( RTYPE, in4, in5, in6, in7, out2, out3 ); \
+}
+#define ILVL_H4_SW( ... ) ILVL_H4( v4i32, __VA_ARGS__ )
+
+/* Description : Interleave left half of word elements from vectors
+ Arguments : Inputs - in0, in1, in2, in3
+ Outputs - out0, out1
+ Return Type - as per RTYPE
+ Details : Left half of word elements of in0 and left half of word
+ elements of in1 are interleaved and copied to out0.
+ Left half of word elements of in2 and left half of word
+ elements of in3 are interleaved and copied to out1.
+*/
+#define ILVL_W2( RTYPE, in0, in1, in2, in3, out0, out1 ) \
+{ \
+ out0 = ( RTYPE ) __msa_ilvl_w( ( v4i32 ) in0, ( v4i32 ) in1 ); \
+ out1 = ( RTYPE ) __msa_ilvl_w( ( v4i32 ) in2, ( v4i32 ) in3 ); \
+}
+#define ILVL_W2_SH( ... ) ILVL_W2( v8i16, __VA_ARGS__ )
+
+/* Description : Interleave right half of byte elements from vectors
+ Arguments : Inputs - in0, in1, in2, in3, in4, in5, in6, in7
+ Outputs - out0, out1, out2, out3
+ Return Type - as per RTYPE
+ Details : Right half of byte elements of in0 and right half of byte
+ elements of in1 are interleaved and copied to out0.
+ Right half of byte elements of in2 and right half of byte
+ elements of in3 are interleaved and copied to out1.
+ Similar for other pairs
+*/
+#define ILVR_B2( RTYPE, in0, in1, in2, in3, out0, out1 ) \
+{ \
+ out0 = ( RTYPE ) __msa_ilvr_b( ( v16i8 ) in0, ( v16i8 ) in1 ); \
+ out1 = ( RTYPE ) __msa_ilvr_b( ( v16i8 ) in2, ( v16i8 ) in3 ); \
+}
+#define ILVR_B2_SB( ... ) ILVR_B2( v16i8, __VA_ARGS__ )
+#define ILVR_B2_UH( ... ) ILVR_B2( v8u16, __VA_ARGS__ )
+#define ILVR_B2_SH( ... ) ILVR_B2( v8i16, __VA_ARGS__ )
+
+#define ILVR_B4( RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
+ out0, out1, out2, out3 ) \
+{ \
+ ILVR_B2( RTYPE, in0, in1, in2, in3, out0, out1 ); \
+ ILVR_B2( RTYPE, in4, in5, in6, in7, out2, out3 ); \
+}
+#define ILVR_B4_UB( ... ) ILVR_B4( v16u8, __VA_ARGS__ )
+#define ILVR_B4_SB( ... ) ILVR_B4( v16i8, __VA_ARGS__ )
+#define ILVR_B4_UH( ... ) ILVR_B4( v8u16, __VA_ARGS__ )
+#define ILVR_B4_SH( ... ) ILVR_B4( v8i16, __VA_ARGS__ )
+
+/* Description : Interleave right half of halfword elements from vectors
+ Arguments : Inputs - in0, in1, in2, in3, in4, in5, in6, in7
+ Outputs - out0, out1, out2, out3
+ Return Type - signed halfword
+ Details : Right half of halfword elements of in0 and right half of
+ halfword elements of in1 are interleaved and copied to out0.
+ Right half of halfword elements of in2 and right half of
+ halfword elements of in3 are interleaved and copied to out1.
+ Similar for other pairs
+*/
+#define ILVR_H2( RTYPE, in0, in1, in2, in3, out0, out1 ) \
+{ \
+ out0 = ( RTYPE ) __msa_ilvr_h( ( v8i16 ) in0, ( v8i16 ) in1 ); \
+ out1 = ( RTYPE ) __msa_ilvr_h( ( v8i16 ) in2, ( v8i16 ) in3 ); \
+}
+#define ILVR_H2_SH( ... ) ILVR_H2( v8i16, __VA_ARGS__ )
+#define ILVR_H2_SW( ... ) ILVR_H2( v4i32, __VA_ARGS__ )
+
+#define ILVR_H4( RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
+ out0, out1, out2, out3 ) \
+{ \
+ ILVR_H2( RTYPE, in0, in1, in2, in3, out0, out1 ); \
+ ILVR_H2( RTYPE, in4, in5, in6, in7, out2, out3 ); \
+}
+#define ILVR_H4_SH( ... ) ILVR_H4( v8i16, __VA_ARGS__ )
+#define ILVR_H4_SW( ... ) ILVR_H4( v4i32, __VA_ARGS__ )
+
+#define ILVR_W2( RTYPE, in0, in1, in2, in3, out0, out1 ) \
+{ \
+ out0 = ( RTYPE ) __msa_ilvr_w( ( v4i32 ) in0, ( v4i32 ) in1 ); \
+ out1 = ( RTYPE ) __msa_ilvr_w( ( v4i32 ) in2, ( v4i32 ) in3 ); \
+}
+#define ILVR_W2_SH( ... ) ILVR_W2( v8i16, __VA_ARGS__ )
+
+/* Description : Interleave right half of double word elements from vectors
+ Arguments : Inputs - in0, in1, in2, in3, in4, in5, in6, in7
+ Outputs - out0, out1, out2, out3
+ Return Type - unsigned double word
+ Details : Right half of double word elements of in0 and right half of
+ double word elements of in1 are interleaved and copied to out0.
+ Right half of double word elements of in2 and right half of
+ double word elements of in3 are interleaved and copied to out1.
+*/
+#define ILVR_D2( RTYPE, in0, in1, in2, in3, out0, out1 ) \
+{ \
+ out0 = ( RTYPE ) __msa_ilvr_d( ( v2i64 ) ( in0 ), ( v2i64 ) ( in1 ) ); \
+ out1 = ( RTYPE ) __msa_ilvr_d( ( v2i64 ) ( in2 ), ( v2i64 ) ( in3 ) ); \
+}
+#define ILVR_D2_UB( ... ) ILVR_D2( v16u8, __VA_ARGS__ )
+#define ILVR_D2_SB( ... ) ILVR_D2( v16i8, __VA_ARGS__ )
+#define ILVR_D2_SH( ... ) ILVR_D2( v8i16, __VA_ARGS__ )
+
+#define ILVR_D4( RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
+ out0, out1, out2, out3 ) \
+{ \
+ ILVR_D2( RTYPE, in0, in1, in2, in3, out0, out1 ); \
+ ILVR_D2( RTYPE, in4, in5, in6, in7, out2, out3 ); \
+}
+#define ILVR_D4_UB( ... ) ILVR_D4( v16u8, __VA_ARGS__ )
+
+/* Description : Interleave both left and right half of input vectors
+ Arguments : Inputs - in0, in1
+ Outputs - out0, out1
+ Return Type - as per RTYPE
+ Details : Right half of byte elements from 'in0' and 'in1' are
+ interleaved and stored to 'out0'
+ Left half of byte elements from 'in0' and 'in1' are
+ interleaved and stored to 'out1'
+*/
+#define ILVRL_B2( RTYPE, in0, in1, out0, out1 ) \
+{ \
+ out0 = ( RTYPE ) __msa_ilvr_b( ( v16i8 ) in0, ( v16i8 ) in1 ); \
+ out1 = ( RTYPE ) __msa_ilvl_b( ( v16i8 ) in0, ( v16i8 ) in1 ); \
+}
+#define ILVRL_B2_UB( ... ) ILVRL_B2( v16u8, __VA_ARGS__ )
+#define ILVRL_B2_SB( ... ) ILVRL_B2( v16i8, __VA_ARGS__ )
+#define ILVRL_B2_UH( ... ) ILVRL_B2( v8u16, __VA_ARGS__ )
+#define ILVRL_B2_SH( ... ) ILVRL_B2( v8i16, __VA_ARGS__ )
+#define ILVRL_B2_SW( ... ) ILVRL_B2( v4i32, __VA_ARGS__ )
+
+#define ILVRL_H2( RTYPE, in0, in1, out0, out1 ) \
+{ \
+ out0 = ( RTYPE ) __msa_ilvr_h( ( v8i16 ) in0, ( v8i16 ) in1 ); \
+ out1 = ( RTYPE ) __msa_ilvl_h( ( v8i16 ) in0, ( v8i16 ) in1 ); \
+}
+#define ILVRL_H2_SH( ... ) ILVRL_H2( v8i16, __VA_ARGS__ )
+#define ILVRL_H2_SW( ... ) ILVRL_H2( v4i32, __VA_ARGS__ )
+
+#define ILVRL_W2( RTYPE, in0, in1, out0, out1 ) \
+{ \
+ out0 = ( RTYPE ) __msa_ilvr_w( ( v4i32 ) in0, ( v4i32 ) in1 ); \
+ out1 = ( RTYPE ) __msa_ilvl_w( ( v4i32 ) in0, ( v4i32 ) in1 ); \
+}
+#define ILVRL_W2_SH( ... ) ILVRL_W2( v8i16, __VA_ARGS__ )
+#define ILVRL_W2_SW( ... ) ILVRL_W2( v4i32, __VA_ARGS__ )
+
+/* Description : Maximum values between signed elements of vector and
+ 5-bit signed immediate value are copied to the output vector
+ Arguments : Inputs - in0, in1, in2, in3, max_val
+ Outputs - in0, in1, in2, in3 ( in place )
+ Return Type - unsigned halfword
+ Details : Maximum of signed halfword element values from 'in0' and
+ 'max_val' are written to output vector 'in0'
+*/
+#define MAXI_SH2( RTYPE, in0, in1, max_val ) \
+{ \
+ in0 = ( RTYPE ) __msa_maxi_s_h( ( v8i16 ) in0, ( max_val ) ); \
+ in1 = ( RTYPE ) __msa_maxi_s_h( ( v8i16 ) in1, ( max_val ) ); \
+}
+#define MAXI_SH2_UH( ... ) MAXI_SH2( v8u16, __VA_ARGS__ )
+#define MAXI_SH2_SH( ... ) MAXI_SH2( v8i16, __VA_ARGS__ )
+
+#define MAXI_SH4( RTYPE, in0, in1, in2, in3, max_val ) \
+{ \
+ MAXI_SH2( RTYPE, in0, in1, max_val ); \
+ MAXI_SH2( RTYPE, in2, in3, max_val ); \
+}
+#define MAXI_SH4_UH( ... ) MAXI_SH4( v8u16, __VA_ARGS__ )
+
+/* Description : Saturate the halfword element values to the max
+ unsigned value of ( sat_val+1 bits )
+ The element data width remains unchanged
+ Arguments : Inputs - in0, in1, in2, in3, sat_val
+ Outputs - in0, in1, in2, in3 ( in place )
+ Return Type - unsigned halfword
+ Details : Each unsigned halfword element from 'in0' is saturated to the
+ value generated with ( sat_val+1 ) bit range
+ Results are in placed to original vectors
+*/
+#define SAT_UH2( RTYPE, in0, in1, sat_val ) \
+{ \
+ in0 = ( RTYPE ) __msa_sat_u_h( ( v8u16 ) in0, sat_val ); \
+ in1 = ( RTYPE ) __msa_sat_u_h( ( v8u16 ) in1, sat_val ); \
+}
+#define SAT_UH2_UH( ... ) SAT_UH2( v8u16, __VA_ARGS__ )
+
+#define SAT_UH4( RTYPE, in0, in1, in2, in3, sat_val ) \
+{ \
+ SAT_UH2( RTYPE, in0, in1, sat_val ); \
+ SAT_UH2( RTYPE, in2, in3, sat_val ) \
+}
+#define SAT_UH4_UH( ... ) SAT_UH4( v8u16, __VA_ARGS__ )
+
+/* Description : Saturate the halfword element values to the max
+ unsigned value of ( sat_val+1 bits )
+ The element data width remains unchanged
+ Arguments : Inputs - in0, in1, in2, in3, sat_val
+ Outputs - in0, in1, in2, in3 ( in place )
+ Return Type - unsigned halfword
+ Details : Each unsigned halfword element from 'in0' is saturated to the
+ value generated with ( sat_val+1 ) bit range
+ Results are in placed to original vectors
+*/
+#define SAT_SH2( RTYPE, in0, in1, sat_val ) \
+{ \
+ in0 = ( RTYPE ) __msa_sat_s_h( ( v8i16 ) in0, sat_val ); \
+ in1 = ( RTYPE ) __msa_sat_s_h( ( v8i16 ) in1, sat_val ); \
+}
+#define SAT_SH2_SH( ... ) SAT_SH2( v8i16, __VA_ARGS__ )
+
+#define SAT_SH4( RTYPE, in0, in1, in2, in3, sat_val ) \
+{ \
+ SAT_SH2( RTYPE, in0, in1, sat_val ); \
+ SAT_SH2( RTYPE, in2, in3, sat_val ); \
+}
+#define SAT_SH4_SH( ... ) SAT_SH4( v8i16, __VA_ARGS__ )
+
+/* Description : Saturate the word element values to the max
+ unsigned value of ( sat_val+1 bits )
+ The element data width remains unchanged
+ Arguments : Inputs - in0, in1, in2, in3, sat_val
+ Outputs - in0, in1, in2, in3 ( in place )
+ Return Type - unsigned word
+ Details : Each unsigned word element from 'in0' is saturated to the
+ value generated with ( sat_val+1 ) bit range
+ Results are in placed to original vectors
+*/
+#define SAT_SW2( RTYPE, in0, in1, sat_val ) \
+{ \
+ in0 = ( RTYPE ) __msa_sat_s_w( ( v4i32 ) in0, sat_val ); \
+ in1 = ( RTYPE ) __msa_sat_s_w( ( v4i32 ) in1, sat_val ); \
+}
+#define SAT_SW2_SW( ... ) SAT_SW2( v4i32, __VA_ARGS__ )
+
+/* Description : Pack even byte elements of vector pairs
+ Arguments : Inputs - in0, in1, in2, in3
+ Outputs - out0, out1
+ Return Type - as per RTYPE
+ Details : Even byte elements of in0 are copied to the left half of
+ out0 & even byte elements of in1 are copied to the right
+ half of out0.
+ Even byte elements of in2 are copied to the left half of
+ out1 & even byte elements of in3 are copied to the right
+ half of out1.
+*/
+#define PCKEV_B2( RTYPE, in0, in1, in2, in3, out0, out1 ) \
+{ \
+ out0 = ( RTYPE ) __msa_pckev_b( ( v16i8 ) in0, ( v16i8 ) in1 ); \
+ out1 = ( RTYPE ) __msa_pckev_b( ( v16i8 ) in2, ( v16i8 ) in3 ); \
+}
+#define PCKEV_B2_SB( ... ) PCKEV_B2( v16i8, __VA_ARGS__ )
+#define PCKEV_B2_UB( ... ) PCKEV_B2( v16u8, __VA_ARGS__ )
+#define PCKEV_B2_SH( ... ) PCKEV_B2( v8i16, __VA_ARGS__ )
+#define PCKEV_B2_SW( ... ) PCKEV_B2( v4i32, __VA_ARGS__ )
+
+#define PCKEV_B3( RTYPE, in0, in1, in2, in3, in4, in5, out0, out1, out2 ) \
+{ \
+ PCKEV_B2( RTYPE, in0, in1, in2, in3, out0, out1 ); \
+ out2 = ( RTYPE ) __msa_pckev_b( ( v16i8 ) in4, ( v16i8 ) in5 ); \
+}
+#define PCKEV_B3_UB( ... ) PCKEV_B3( v16u8, __VA_ARGS__ )
+
+#define PCKEV_B4( RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
+ out0, out1, out2, out3 ) \
+{ \
+ PCKEV_B2( RTYPE, in0, in1, in2, in3, out0, out1 ); \
+ PCKEV_B2( RTYPE, in4, in5, in6, in7, out2, out3 ); \
+}
+#define PCKEV_B4_SB( ... ) PCKEV_B4( v16i8, __VA_ARGS__ )
+#define PCKEV_B4_UB( ... ) PCKEV_B4( v16u8, __VA_ARGS__ )
+
+/* Description : Pack even halfword elements of vector pairs
+ Arguments : Inputs - in0, in1, in2, in3
+ Outputs - out0, out1
+ Return Type - as per RTYPE
+ Details : Even halfword elements of in0 are copied to the left half of
+ out0 & even halfword elements of in1 are copied to the right
+ half of out0.
+ Even halfword elements of in2 are copied to the left half of
+ out1 & even halfword elements of in3 are copied to the right
+ half of out1.
+*/
+#define PCKEV_H2( RTYPE, in0, in1, in2, in3, out0, out1 ) \
+{ \
+ out0 = ( RTYPE ) __msa_pckev_h( ( v8i16 ) in0, ( v8i16 ) in1 ); \
+ out1 = ( RTYPE ) __msa_pckev_h( ( v8i16 ) in2, ( v8i16 ) in3 ); \
+}
+#define PCKEV_H2_SH( ... ) PCKEV_H2( v8i16, __VA_ARGS__ )
+
+#define PCKEV_H4( RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
+ out0, out1, out2, out3 ) \
+{ \
+ PCKEV_H2( RTYPE, in0, in1, in2, in3, out0, out1 ); \
+ PCKEV_H2( RTYPE, in4, in5, in6, in7, out2, out3 ); \
+}
+#define PCKEV_H4_SH( ... ) PCKEV_H4( v8i16, __VA_ARGS__ )
+
+/* Description : Pack even double word elements of vector pairs
+ Arguments : Inputs - in0, in1, in2, in3
+ Outputs - out0, out1
+ Return Type - unsigned byte
+ Details : Even double elements of in0 are copied to the left half of
+ out0 & even double elements of in1 are copied to the right
+ half of out0.
+ Even double elements of in2 are copied to the left half of
+ out1 & even double elements of in3 are copied to the right
+ half of out1.
+*/
+#define PCKEV_D2( RTYPE, in0, in1, in2, in3, out0, out1 ) \
+{ \
+ out0 = ( RTYPE ) __msa_pckev_d( ( v2i64 ) in0, ( v2i64 ) in1 ); \
+ out1 = ( RTYPE ) __msa_pckev_d( ( v2i64 ) in2, ( v2i64 ) in3 ); \
+}
+#define PCKEV_D2_UB( ... ) PCKEV_D2( v16u8, __VA_ARGS__ )
+
+#define PCKEV_D4( RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
+ out0, out1, out2, out3 ) \
+{ \
+ PCKEV_D2( RTYPE, in0, in1, in2, in3, out0, out1 ); \
+ PCKEV_D2( RTYPE, in4, in5, in6, in7, out2, out3 ); \
+}
+#define PCKEV_D4_UB( ... ) PCKEV_D4( v16u8, __VA_ARGS__ )
+
+/* Description : Pack odd byte elements of vector pairs
+ Arguments : Inputs - in0, in1, in2, in3
+ Outputs - out0, out1
+ Return Type - unsigned byte
+ Details : Odd byte elements of in0 are copied to the left half of
+ out0 & odd byte elements of in1 are copied to the right
+ half of out0.
+ Odd byte elements of in2 are copied to the left half of
+ out1 & odd byte elements of in3 are copied to the right
+ half of out1.
+*/
+#define PCKOD_B2( RTYPE, in0, in1, in2, in3, out0, out1 ) \
+{ \
+ out0 = ( RTYPE ) __msa_pckod_b( ( v16i8 ) in0, ( v16i8 ) in1 ); \
+ out1 = ( RTYPE ) __msa_pckod_b( ( v16i8 ) in2, ( v16i8 ) in3 ); \
+}
+#define PCKOD_B2_UB( ... ) PCKOD_B2( v16u8, __VA_ARGS__ )
+
+#define PCKOD_B4( RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
+ out0, out1, out2, out3 ) \
+{ \
+ PCKOD_B2( RTYPE, in0, in1, in2, in3, out0, out1 ); \
+ PCKOD_B2( RTYPE, in4, in5, in6, in7, out2, out3 ); \
+}
+#define PCKOD_B4_UB( ... ) PCKOD_B4( v16u8, __VA_ARGS__ )
+
+/* Description : Pack odd double word elements of vector pairs
+ Arguments : Inputs - in0, in1
+ Outputs - out0, out1
+ Return Type - as per RTYPE
+ Details : As operation is on same input 'in0' vector, index 1 double word
+ element is overwritten to index 0 and result is written to out0
+ As operation is on same input 'in1' vector, index 1 double word
+ element is overwritten to index 0 and result is written to out1
+*/
+#define PCKOD_D2( RTYPE, in0, in1, in2, in3, out0, out1 ) \
+{ \
+ out0 = ( RTYPE ) __msa_pckod_d( ( v2i64 ) in0, ( v2i64 ) in1 ); \
+ out1 = ( RTYPE ) __msa_pckod_d( ( v2i64 ) in2, ( v2i64 ) in3 ); \
+}
+#define PCKOD_D2_SH( ... ) PCKOD_D2( v8i16, __VA_ARGS__ )
+#define PCKOD_D2_SD( ... ) PCKOD_D2( v2i64, __VA_ARGS__ )
+
+/* Description : Each byte element is logically xor'ed with immediate 128
+ Arguments : Inputs - in0, in1
+ Outputs - in0, in1 ( in-place )
+ Return Type - as per RTYPE
+ Details : Each unsigned byte element from input vector 'in0' is
+ logically xor'ed with 128 and result is in-place stored in
+ 'in0' vector
+ Each unsigned byte element from input vector 'in1' is
+ logically xor'ed with 128 and result is in-place stored in
+ 'in1' vector
+ Similar for other pairs
+*/
+#define XORI_B2_128( RTYPE, in0, in1 ) \
+{ \
+ in0 = ( RTYPE ) __msa_xori_b( ( v16u8 ) in0, 128 ); \
+ in1 = ( RTYPE ) __msa_xori_b( ( v16u8 ) in1, 128 ); \
+}
+#define XORI_B2_128_UB( ... ) XORI_B2_128( v16u8, __VA_ARGS__ )
+#define XORI_B2_128_SB( ... ) XORI_B2_128( v16i8, __VA_ARGS__ )
+
+#define XORI_B3_128( RTYPE, in0, in1, in2 ) \
+{ \
+ XORI_B2_128( RTYPE, in0, in1 ); \
+ in2 = ( RTYPE ) __msa_xori_b( ( v16u8 ) in2, 128 ); \
+}
+#define XORI_B3_128_SB( ... ) XORI_B3_128( v16i8, __VA_ARGS__ )
+
+#define XORI_B4_128( RTYPE, in0, in1, in2, in3 ) \
+{ \
+ XORI_B2_128( RTYPE, in0, in1 ); \
+ XORI_B2_128( RTYPE, in2, in3 ); \
+}
+#define XORI_B4_128_UB( ... ) XORI_B4_128( v16u8, __VA_ARGS__ )
+#define XORI_B4_128_SB( ... ) XORI_B4_128( v16i8, __VA_ARGS__ )
+
+#define XORI_B5_128( RTYPE, in0, in1, in2, in3, in4 ) \
+{ \
+ XORI_B3_128( RTYPE, in0, in1, in2 ); \
+ XORI_B2_128( RTYPE, in3, in4 ); \
+}
+#define XORI_B5_128_SB( ... ) XORI_B5_128( v16i8, __VA_ARGS__ )
+
+/* Description : Addition of signed halfword elements and signed saturation
+ Arguments : Inputs - in0, in1, in2, in3
+ Outputs - out0, out1
+ Return Type - as per RTYPE
+ Details : Signed halfword elements from 'in0' are added to signed
+ halfword elements of 'in1'. The result is then signed saturated
+ between -32768 to +32767 ( as per halfword data type )
+ Similar for other pairs
+*/
+#define ADDS_SH2( RTYPE, in0, in1, in2, in3, out0, out1 ) \
+{ \
+ out0 = ( RTYPE ) __msa_adds_s_h( ( v8i16 ) in0, ( v8i16 ) in1 ); \
+ out1 = ( RTYPE ) __msa_adds_s_h( ( v8i16 ) in2, ( v8i16 ) in3 ); \
+}
+#define ADDS_SH2_SH( ... ) ADDS_SH2( v8i16, __VA_ARGS__ )
+
+#define ADDS_SH4( RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
+ out0, out1, out2, out3 ) \
+{ \
+ ADDS_SH2( RTYPE, in0, in1, in2, in3, out0, out1 ); \
+ ADDS_SH2( RTYPE, in4, in5, in6, in7, out2, out3 ); \
+}
+#define ADDS_SH4_UH( ... ) ADDS_SH4( v8u16, __VA_ARGS__ )
+
+/* Description : Shift left all elements of vector ( generic for all data types )
+ Arguments : Inputs - in0, in1, in2, in3, shift
+ Outputs - in0, in1, in2, in3 ( in place )
+ Return Type - as per input vector RTYPE
+ Details : Each element of vector 'in0' is left shifted by 'shift' and
+ result is in place written to 'in0'
+ Similar for other pairs
+*/
+#define SLLI_4V( in0, in1, in2, in3, shift ) \
+{ \
+ in0 = in0 << shift; \
+ in1 = in1 << shift; \
+ in2 = in2 << shift; \
+ in3 = in3 << shift; \
+}
+
+/* Description : Arithmetic shift right all elements of vector
+ ( generic for all data types )
+ Arguments : Inputs - in0, in1, in2, in3, shift
+ Outputs - in0, in1, in2, in3 ( in place )
+ Return Type - as per input vector RTYPE
+ Details : Each element of vector 'in0' is right shifted by 'shift' and
+ result is in place written to 'in0'
+ Here, 'shift' is GP variable passed in
+ Similar for other pairs
+*/
+#define SRA_4V( in0, in1, in2, in3, shift ) \
+{ \
+ in0 = in0 >> shift; \
+ in1 = in1 >> shift; \
+ in2 = in2 >> shift; \
+ in3 = in3 >> shift; \
+}
+
+/* Description : Shift right arithmetic rounded halfwords
+ Arguments : Inputs - in0, in1, shift
+ Outputs - in0, in1, (in place)
+ Return Type - unsigned halfword
+ Details : Each element of vector 'in0' is shifted right arithmetic by
+ number of bits respective element holds in vector 'shift'.
+ The last discarded bit is added to shifted value for rounding
+ and the result is in place written to 'in0'
+ Here, 'shift' is a vector passed in
+ Similar for other pairs
+*/
+#define SRAR_H2( RTYPE, in0, in1, shift ) \
+{ \
+ in0 = ( RTYPE ) __msa_srar_h( ( v8i16 ) in0, ( v8i16 ) shift ); \
+ in1 = ( RTYPE ) __msa_srar_h( ( v8i16 ) in1, ( v8i16 ) shift ); \
+}
+#define SRAR_H2_SH( ... ) SRAR_H2( v8i16, __VA_ARGS__ )
+
+#define SRAR_H4( RTYPE, in0, in1, in2, in3, shift ) \
+{ \
+ SRAR_H2( RTYPE, in0, in1, shift ) \
+ SRAR_H2( RTYPE, in2, in3, shift ) \
+}
+#define SRAR_H4_SH( ... ) SRAR_H4( v8i16, __VA_ARGS__ )
+
+/* Description : Shift right logical all halfword elements of vector
+ Arguments : Inputs - in0, in1, in2, in3, shift
+ Outputs - in0, in1, in2, in3 ( in place )
+ Return Type - unsigned halfword
+ Details : Each element of vector 'in0' is shifted right logical by
+ number of bits respective element holds in vector 'shift' and
+ result is in place written to 'in0'
+ Here, 'shift' is a vector passed in
+ Similar for other pairs
+*/
+#define SRL_H4( RTYPE, in0, in1, in2, in3, shift ) \
+{ \
+ in0 = ( RTYPE ) __msa_srl_h( ( v8i16 ) in0, ( v8i16 ) shift ); \
+ in1 = ( RTYPE ) __msa_srl_h( ( v8i16 ) in1, ( v8i16 ) shift ); \
+ in2 = ( RTYPE ) __msa_srl_h( ( v8i16 ) in2, ( v8i16 ) shift ); \
+ in3 = ( RTYPE ) __msa_srl_h( ( v8i16 ) in3, ( v8i16 ) shift ); \
+}
+#define SRL_H4_UH( ... ) SRL_H4( v8u16, __VA_ARGS__ )
+
+/* Description : Shift right arithmetic rounded ( immediate )
+ Arguments : Inputs - in0, in1, in2, in3, shift
+ Outputs - in0, in1, in2, in3 ( in place )
+ Return Type - as per RTYPE
+ Details : Each element of vector 'in0' is shifted right arithmetic by
+ value in 'shift'.
+ The last discarded bit is added to shifted value for rounding
+ and the result is in place written to 'in0'
+ Similar for other pairs
+*/
+#define SRARI_H2( RTYPE, in0, in1, shift ) \
+{ \
+ in0 = ( RTYPE ) __msa_srari_h( ( v8i16 ) in0, shift ); \
+ in1 = ( RTYPE ) __msa_srari_h( ( v8i16 ) in1, shift ); \
+}
+#define SRARI_H2_UH( ... ) SRARI_H2( v8u16, __VA_ARGS__ )
+#define SRARI_H2_SH( ... ) SRARI_H2( v8i16, __VA_ARGS__ )
+
+#define SRARI_H4( RTYPE, in0, in1, in2, in3, shift ) \
+{ \
+ SRARI_H2( RTYPE, in0, in1, shift ); \
+ SRARI_H2( RTYPE, in2, in3, shift ); \
+}
+#define SRARI_H4_UH( ... ) SRARI_H4( v8u16, __VA_ARGS__ )
+#define SRARI_H4_SH( ... ) SRARI_H4( v8i16, __VA_ARGS__ )
+
+/* Description : Shift right arithmetic rounded ( immediate )
+ Arguments : Inputs - in0, in1, shift
+ Outputs - in0, in1 ( in place )
+ Return Type - as per RTYPE
+ Details : Each element of vector 'in0' is shifted right arithmetic by
+ value in 'shift'.
+ The last discarded bit is added to shifted value for rounding
+ and the result is in place written to 'in0'
+ Similar for other pairs
+*/
+#define SRARI_W2( RTYPE, in0, in1, shift ) \
+{ \
+ in0 = ( RTYPE ) __msa_srari_w( ( v4i32 ) in0, shift ); \
+ in1 = ( RTYPE ) __msa_srari_w( ( v4i32 ) in1, shift ); \
+}
+#define SRARI_W2_SW( ... ) SRARI_W2( v4i32, __VA_ARGS__ )
+
+#define SRARI_W4( RTYPE, in0, in1, in2, in3, shift ) \
+{ \
+ SRARI_W2( RTYPE, in0, in1, shift ); \
+ SRARI_W2( RTYPE, in2, in3, shift ); \
+}
+#define SRARI_W4_SW( ... ) SRARI_W4( v4i32, __VA_ARGS__ )
+
+/* Description : Multiplication of pairs of vectors
+ Arguments : Inputs - in0, in1, in2, in3
+ Outputs - out0, out1
+ Details : Each element from 'in0' is multiplied with elements from 'in1'
+ and result is written to 'out0'
+ Similar for other pairs
+*/
+#define MUL2( in0, in1, in2, in3, out0, out1 ) \
+{ \
+ out0 = in0 * in1; \
+ out1 = in2 * in3; \
+}
+#define MUL4( in0, in1, in2, in3, in4, in5, in6, in7, \
+ out0, out1, out2, out3 ) \
+{ \
+ MUL2( in0, in1, in2, in3, out0, out1 ); \
+ MUL2( in4, in5, in6, in7, out2, out3 ); \
+}
+
+/* Description : Addition of 2 pairs of vectors
+ Arguments : Inputs - in0, in1, in2, in3
+ Outputs - out0, out1
+ Details : Each element from 2 pairs vectors is added and 2 results are
+ produced
+*/
+#define ADD2( in0, in1, in2, in3, out0, out1 ) \
+{ \
+ out0 = in0 + in1; \
+ out1 = in2 + in3; \
+}
+#define ADD4( in0, in1, in2, in3, in4, in5, in6, in7, \
+ out0, out1, out2, out3 ) \
+{ \
+ ADD2( in0, in1, in2, in3, out0, out1 ); \
+ ADD2( in4, in5, in6, in7, out2, out3 ); \
+}
+
+#define SUB4( in0, in1, in2, in3, in4, in5, in6, in7, \
+ out0, out1, out2, out3 ) \
+{ \
+ out0 = in0 - in1; \
+ out1 = in2 - in3; \
+ out2 = in4 - in5; \
+ out3 = in6 - in7; \
+}
+
+/* Description : Sign extend halfword elements from right half of the vector
+ Arguments : Inputs - in ( input halfword vector )
+ Outputs - out ( sign extended word vectors )
+ Return Type - signed word
+ Details : Sign bit of halfword elements from input vector 'in' is
+ extracted and interleaved with same vector 'in0' to generate
+ 4 word elements keeping sign intact
+*/
+#define UNPCK_R_SH_SW( in, out ) \
+{ \
+ v8i16 sign_m; \
+ \
+ sign_m = __msa_clti_s_h( ( v8i16 ) in, 0 ); \
+ out = ( v4i32 ) __msa_ilvr_h( sign_m, ( v8i16 ) in ); \
+}
+
+/* Description : Zero extend unsigned byte elements to halfword elements
+ Arguments : Inputs - in ( 1 input unsigned byte vector )
+ Outputs - out0, out1 ( unsigned 2 halfword vectors )
+ Return Type - signed halfword
+ Details : Zero extended right half of vector is returned in 'out0'
+ Zero extended left half of vector is returned in 'out1'
+*/
+#define UNPCK_UB_SH( in, out0, out1 ) \
+{ \
+ v16i8 zero_m = { 0 }; \
+ \
+ ILVRL_B2_SH( zero_m, in, out0, out1 ); \
+}
+
+/* Description : Sign extend halfword elements from input vector and return
+ result in pair of vectors
+ Arguments : Inputs - in ( 1 input halfword vector )
+ Outputs - out0, out1 ( sign extended 2 word vectors )
+ Return Type - signed word
+ Details : Sign bit of halfword elements from input vector 'in' is
+ extracted and interleaved right with same vector 'in0' to
+ generate 4 signed word elements in 'out0'
+ Then interleaved left with same vector 'in0' to
+ generate 4 signed word elements in 'out1'
+*/
+#define UNPCK_SH_SW( in, out0, out1 ) \
+{ \
+ v8i16 tmp_m; \
+ \
+ tmp_m = __msa_clti_s_h( ( v8i16 ) in, 0 ); \
+ ILVRL_H2_SW( tmp_m, in, out0, out1 ); \
+}
+
+/* Description : Butterfly of 4 input vectors
+ Arguments : Inputs - in0, in1, in2, in3
+ Outputs - out0, out1, out2, out3
+ Details : Butterfly operation
+*/
+#define BUTTERFLY_4( in0, in1, in2, in3, out0, out1, out2, out3 ) \
+{ \
+ out0 = in0 + in3; \
+ out1 = in1 + in2; \
+ \
+ out2 = in1 - in2; \
+ out3 = in0 - in3; \
+}
+
+/* Description : Butterfly of 8 input vectors
+ Arguments : Inputs - in0 ... in7
+ Outputs - out0 .. out7
+ Details : Butterfly operation
+*/
+#define BUTTERFLY_8( in0, in1, in2, in3, in4, in5, in6, in7, \
+ out0, out1, out2, out3, out4, out5, out6, out7 ) \
+{ \
+ out0 = in0 + in7; \
+ out1 = in1 + in6; \
+ out2 = in2 + in5; \
+ out3 = in3 + in4; \
+ \
+ out4 = in3 - in4; \
+ out5 = in2 - in5; \
+ out6 = in1 - in6; \
+ out7 = in0 - in7; \
+}
+
+/* Description : Transposes 4x4 block with half word elements in vectors
+ Arguments : Inputs - in0, in1, in2, in3
+ Outputs - out0, out1, out2, out3
+ Return Type - signed halfword
+ Details :
+*/
+#define TRANSPOSE4x4_SH_SH( in0, in1, in2, in3, out0, out1, out2, out3 ) \
+{ \
+ v8i16 s0_m, s1_m; \
+ \
+ ILVR_H2_SH( in1, in0, in3, in2, s0_m, s1_m ); \
+ ILVRL_W2_SH( s1_m, s0_m, out0, out2 ); \
+ out1 = ( v8i16 ) __msa_ilvl_d( ( v2i64 ) out0, ( v2i64 ) out0 ); \
+ out3 = ( v8i16 ) __msa_ilvl_d( ( v2i64 ) out0, ( v2i64 ) out2 ); \
+}
+
+/* Description : Transposes 8x8 block with half word elements in vectors
+ Arguments : Inputs - in0, in1, in2, in3, in4, in5, in6, in7
+ Outputs - out0, out1, out2, out3, out4, out5, out6, out7
+ Return Type - signed halfword
+ Details :
+*/
+#define TRANSPOSE8x8_H( RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
+ out0, out1, out2, out3, out4, out5, out6, out7 ) \
+{ \
+ v8i16 s0_m, s1_m; \
+ v8i16 tmp0_m, tmp1_m, tmp2_m, tmp3_m; \
+ v8i16 tmp4_m, tmp5_m, tmp6_m, tmp7_m; \
+ \
+ ILVR_H2_SH( in6, in4, in7, in5, s0_m, s1_m ); \
+ ILVRL_H2_SH( s1_m, s0_m, tmp0_m, tmp1_m ); \
+ ILVL_H2_SH( in6, in4, in7, in5, s0_m, s1_m ); \
+ ILVRL_H2_SH( s1_m, s0_m, tmp2_m, tmp3_m ); \
+ ILVR_H2_SH( in2, in0, in3, in1, s0_m, s1_m ); \
+ ILVRL_H2_SH( s1_m, s0_m, tmp4_m, tmp5_m ); \
+ ILVL_H2_SH( in2, in0, in3, in1, s0_m, s1_m ); \
+ ILVRL_H2_SH( s1_m, s0_m, tmp6_m, tmp7_m ); \
+ PCKEV_D4( RTYPE, tmp0_m, tmp4_m, tmp1_m, tmp5_m, tmp2_m, tmp6_m, \
+ tmp3_m, tmp7_m, out0, out2, out4, out6 ); \
+ out1 = ( RTYPE ) __msa_pckod_d( ( v2i64 ) tmp0_m, ( v2i64 ) tmp4_m ); \
+ out3 = ( RTYPE ) __msa_pckod_d( ( v2i64 ) tmp1_m, ( v2i64 ) tmp5_m ); \
+ out5 = ( RTYPE ) __msa_pckod_d( ( v2i64 ) tmp2_m, ( v2i64 ) tmp6_m ); \
+ out7 = ( RTYPE ) __msa_pckod_d( ( v2i64 ) tmp3_m, ( v2i64 ) tmp7_m ); \
+}
+#define TRANSPOSE8x8_SH_SH( ... ) TRANSPOSE8x8_H( v8i16, __VA_ARGS__ )
+
+/* Description : Transposes 4x4 block with word elements in vectors
+ Arguments : Inputs - in0, in1, in2, in3
+ Outputs - out0, out1, out2, out3
+ Return Type - signed word
+ Details :
+*/
+#define TRANSPOSE4x4_SW_SW( in0, in1, in2, in3, out0, out1, out2, out3 ) \
+{ \
+ v4i32 s0_m, s1_m, s2_m, s3_m; \
+ \
+ ILVRL_W2_SW( in1, in0, s0_m, s1_m ); \
+ ILVRL_W2_SW( in3, in2, s2_m, s3_m ); \
+ \
+ out0 = ( v4i32 ) __msa_ilvr_d( ( v2i64 ) s2_m, ( v2i64 ) s0_m ); \
+ out1 = ( v4i32 ) __msa_ilvl_d( ( v2i64 ) s2_m, ( v2i64 ) s0_m ); \
+ out2 = ( v4i32 ) __msa_ilvr_d( ( v2i64 ) s3_m, ( v2i64 ) s1_m ); \
+ out3 = ( v4i32 ) __msa_ilvl_d( ( v2i64 ) s3_m, ( v2i64 ) s1_m ); \
+}
+
+/* Description : Add block 4x4
+ Arguments : Inputs - in0, in1, in2, in3, p_dst, stride
+ Outputs -
+ Return Type - unsigned bytes
+ Details : Least significant 4 bytes from each input vector are added to
+ the destination bytes, clipped between 0-255 and then stored.
+*/
+#define ADDBLK_ST4x4_UB( in0, in1, in2, in3, p_dst, stride ) \
+{ \
+ uint32_t src0_m, src1_m, src2_m, src3_m; \
+ uint32_t out0_m, out1_m, out2_m, out3_m; \
+ v8i16 inp0_m, inp1_m, res0_m, res1_m; \
+ v16i8 dst0_m = { 0 }; \
+ v16i8 dst1_m = { 0 }; \
+ v16i8 zero_m = { 0 }; \
+ \
+ ILVR_D2_SH( in1, in0, in3, in2, inp0_m, inp1_m ) \
+ LW4( p_dst, stride, src0_m, src1_m, src2_m, src3_m ); \
+ INSERT_W2_SB( src0_m, src1_m, dst0_m ); \
+ INSERT_W2_SB( src2_m, src3_m, dst1_m ); \
+ ILVR_B2_SH( zero_m, dst0_m, zero_m, dst1_m, res0_m, res1_m ); \
+ ADD2( res0_m, inp0_m, res1_m, inp1_m, res0_m, res1_m ); \
+ CLIP_SH2_0_255( res0_m, res1_m ); \
+ PCKEV_B2_SB( res0_m, res0_m, res1_m, res1_m, dst0_m, dst1_m ); \
+ \
+ out0_m = __msa_copy_u_w( ( v4i32 ) dst0_m, 0 ); \
+ out1_m = __msa_copy_u_w( ( v4i32 ) dst0_m, 1 ); \
+ out2_m = __msa_copy_u_w( ( v4i32 ) dst1_m, 0 ); \
+ out3_m = __msa_copy_u_w( ( v4i32 ) dst1_m, 1 ); \
+ SW4( out0_m, out1_m, out2_m, out3_m, p_dst, stride ); \
+}
+
+#endif /* X264_MIPS_MACROS_H */
\ No newline at end of file
--
2.3.7
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