[x265-commits] [x265] asm: assembly code for IntraPredAng4x4 Mode 4 & 32
Min Chen
chenm003 at 163.com
Thu Dec 5 05:45:16 CET 2013
details: http://hg.videolan.org/x265/rev/d4fe3e90aebf
branches:
changeset: 5476:d4fe3e90aebf
user: Min Chen <chenm003 at 163.com>
date: Wed Dec 04 13:16:40 2013 +0800
description:
asm: assembly code for IntraPredAng4x4 Mode 4 & 32
Subject: [x265] asm: ALIGN branch target to improvement performance
details: http://hg.videolan.org/x265/rev/f35737d6abfe
branches:
changeset: 5477:f35737d6abfe
user: Min Chen <chenm003 at 163.com>
date: Wed Dec 04 13:27:53 2013 +0800
description:
asm: ALIGN branch target to improvement performance
Subject: [x265] asm: assembly code for IntraPredAng4x4 Mode 5 & 31
details: http://hg.videolan.org/x265/rev/f6dbd8dcec6c
branches:
changeset: 5478:f6dbd8dcec6c
user: Min Chen <chenm003 at 163.com>
date: Wed Dec 04 13:32:13 2013 +0800
description:
asm: assembly code for IntraPredAng4x4 Mode 5 & 31
Subject: [x265] asm: assembly code for IntraPredAng4x4 Mode 6 & 30
details: http://hg.videolan.org/x265/rev/2275a3803a80
branches:
changeset: 5479:2275a3803a80
user: Min Chen <chenm003 at 163.com>
date: Wed Dec 04 13:41:54 2013 +0800
description:
asm: assembly code for IntraPredAng4x4 Mode 6 & 30
Subject: [x265] asm: assembly code for IntraPredAng4x4 Mode 7 & 29
details: http://hg.videolan.org/x265/rev/2f49dab61e52
branches:
changeset: 5480:2f49dab61e52
user: Min Chen <chenm003 at 163.com>
date: Wed Dec 04 13:55:22 2013 +0800
description:
asm: assembly code for IntraPredAng4x4 Mode 7 & 29
Subject: [x265] asm: assembly code for IntraPredAng4x4 Mode 8 & 28
details: http://hg.videolan.org/x265/rev/e37b4badaaa4
branches:
changeset: 5481:e37b4badaaa4
user: Min Chen <chenm003 at 163.com>
date: Wed Dec 04 13:59:20 2013 +0800
description:
asm: assembly code for IntraPredAng4x4 Mode 8 & 28
Subject: [x265] asm: assembly code for IntraPredAng4x4 Mode 9 & 27
details: http://hg.videolan.org/x265/rev/f8d0c7b5b502
branches:
changeset: 5482:f8d0c7b5b502
user: Min Chen <chenm003 at 163.com>
date: Wed Dec 04 14:08:58 2013 +0800
description:
asm: assembly code for IntraPredAng4x4 Mode 9 & 27
Subject: [x265] asm: assembly code for IntraPredAng4x4 Mode 10
details: http://hg.videolan.org/x265/rev/d142d2ba7168
branches:
changeset: 5483:d142d2ba7168
user: Min Chen <chenm003 at 163.com>
date: Wed Dec 04 16:01:27 2013 +0800
description:
asm: assembly code for IntraPredAng4x4 Mode 10
Subject: [x265] asm: assembly code for IntraPredAng4x4 Mode 26
details: http://hg.videolan.org/x265/rev/346830caf664
branches:
changeset: 5484:346830caf664
user: Min Chen <chenm003 at 163.com>
date: Wed Dec 04 16:33:23 2013 +0800
description:
asm: assembly code for IntraPredAng4x4 Mode 26
Subject: [x265] 16bpp: assembly code for sad_NxN functions
details: http://hg.videolan.org/x265/rev/3602d193676d
branches:
changeset: 5485:3602d193676d
user: Dnyaneshwar G <dnyaneshwar at multicorewareinc.com>
date: Wed Dec 04 14:13:58 2013 +0550
description:
16bpp: assembly code for sad_NxN functions
Subject: [x265] asm: 10bpp code for transpose 16x16
details: http://hg.videolan.org/x265/rev/32bac98d3605
branches:
changeset: 5486:32bac98d3605
user: Murugan Vairavel <murugan at multicorewareinc.com>
date: Wed Dec 04 14:36:19 2013 +0550
description:
asm: 10bpp code for transpose 16x16
Subject: [x265] 16bpp: enabled avt32to16_shr and cvt16to32_shl assembly code
details: http://hg.videolan.org/x265/rev/c38d2f74432f
branches:
changeset: 5487:c38d2f74432f
user: Dnyaneshwar G <dnyaneshwar at multicorewareinc.com>
date: Wed Dec 04 14:43:18 2013 +0550
description:
16bpp: enabled avt32to16_shr and cvt16to32_shl assembly code
Subject: [x265] asm: 10bpp code for transpose 32x32
details: http://hg.videolan.org/x265/rev/146aae425df2
branches:
changeset: 5488:146aae425df2
user: Murugan Vairavel <murugan at multicorewareinc.com>
date: Wed Dec 04 15:03:17 2013 +0550
description:
asm: 10bpp code for transpose 32x32
Subject: [x265] asm: 16bpp asm code for pixel_sa8d_16xN
details: http://hg.videolan.org/x265/rev/4547d3d03d1e
branches:
changeset: 5489:4547d3d03d1e
user: Yuvaraj Venkatesh <yuvaraj at multicorewareinc.com>
date: Wed Dec 04 15:09:42 2013 +0550
description:
asm: 16bpp asm code for pixel_sa8d_16xN
Subject: [x265] asm: 10bpp code for transpose 64x64
details: http://hg.videolan.org/x265/rev/f697c98cb63f
branches:
changeset: 5490:f697c98cb63f
user: Murugan Vairavel <murugan at multicorewareinc.com>
date: Wed Dec 04 15:23:19 2013 +0550
description:
asm: 10bpp code for transpose 64x64
Subject: [x265] asm: move constant to const-a.asm
details: http://hg.videolan.org/x265/rev/9b062eb8124e
branches:
changeset: 5491:9b062eb8124e
user: Dnyaneshwar G <dnyaneshwar at multicorewareinc.com>
date: Wed Dec 04 14:54:59 2013 +0550
description:
asm: move constant to const-a.asm
Subject: [x265] asm: 16bpp support for sa8d - 24x32 and 48x64
details: http://hg.videolan.org/x265/rev/61c46e787877
branches:
changeset: 5492:61c46e787877
user: Yuvaraj Venkatesh <yuvaraj at multicorewareinc.com>
date: Wed Dec 04 19:39:58 2013 +0550
description:
asm: 16bpp support for sa8d - 24x32 and 48x64
Subject: [x265] asm: 10bpp code for enabling ssim_end_4
details: http://hg.videolan.org/x265/rev/d73d32097efc
branches:
changeset: 5493:d73d32097efc
user: Murugan Vairavel <murugan at multicorewareinc.com>
date: Wed Dec 04 19:36:06 2013 +0550
description:
asm: 10bpp code for enabling ssim_end_4
Subject: [x265] asm: 16bpp support for sa8d_32xN
details: http://hg.videolan.org/x265/rev/2b6d31ae96e1
branches:
changeset: 5494:2b6d31ae96e1
user: Yuvaraj Venkatesh <yuvaraj at multicorewareinc.com>
date: Wed Dec 04 19:50:11 2013 +0550
description:
asm: 16bpp support for sa8d_32xN
Subject: [x265] asm: 16bpp support for sa8d_64xN
details: http://hg.videolan.org/x265/rev/6aaea628af95
branches:
changeset: 5495:6aaea628af95
user: Yuvaraj Venkatesh <yuvaraj at multicorewareinc.com>
date: Wed Dec 04 20:05:20 2013 +0550
description:
asm: 16bpp support for sa8d_64xN
Subject: [x265] asm: 10bpp code for scale1D_128to64 module
details: http://hg.videolan.org/x265/rev/58674cdab926
branches:
changeset: 5496:58674cdab926
user: Murugan Vairavel <murugan at multicorewareinc.com>
date: Wed Dec 04 21:14:25 2013 +0550
description:
asm: 10bpp code for scale1D_128to64 module
Subject: [x265] fix crash in ssim_end testbench, the x264 support 10bpp only, but testbench use 12bpp
details: http://hg.videolan.org/x265/rev/0716a8ca46b4
branches:
changeset: 5497:0716a8ca46b4
user: Min Chen <chenm003 at 163.com>
date: Wed Dec 04 22:50:18 2013 +0800
description:
fix crash in ssim_end testbench, the x264 support 10bpp only, but testbench use 12bpp
Subject: [x265] Merge
details: http://hg.videolan.org/x265/rev/2f41fae4a776
branches:
changeset: 5498:2f41fae4a776
user: Steve Borho <steve at borho.org>
date: Wed Dec 04 11:34:24 2013 -0600
description:
Merge
Subject: [x265] vec: drop 16bpp sad vector intrinsics, we have ASM coverage
details: http://hg.videolan.org/x265/rev/304354e736dc
branches:
changeset: 5499:304354e736dc
user: Steve Borho <steve at borho.org>
date: Wed Dec 04 11:47:31 2013 -0600
description:
vec: drop 16bpp sad vector intrinsics, we have ASM coverage
Subject: [x265] remove Agner Fog's vector classes and their last few users
details: http://hg.videolan.org/x265/rev/421a37d0924d
branches:
changeset: 5500:421a37d0924d
user: Steve Borho <steve at borho.org>
date: Wed Dec 04 12:47:16 2013 -0600
description:
remove Agner Fog's vector classes and their last few users
We'll take a step back for HIGH_BIT_DEPTH perf for a few days, but these
functions are all expected to have assembly coverage soon. This allows us to
remove a few hacks from our cmake scripts as well.
Subject: [x265] ipfilterharness: do not test chroma for i400 color space
details: http://hg.videolan.org/x265/rev/716ec3505f43
branches:
changeset: 5501:716ec3505f43
user: Steve Borho <steve at borho.org>
date: Wed Dec 04 13:01:09 2013 -0600
description:
ipfilterharness: do not test chroma for i400 color space
Because, umh, it doesn't have any chroma channels
Subject: [x265] oops
details: http://hg.videolan.org/x265/rev/834d6f7608c1
branches:
changeset: 5502:834d6f7608c1
user: Steve Borho <steve at borho.org>
date: Wed Dec 04 13:05:46 2013 -0600
description:
oops
Subject: [x265] encoder: remove trailing white-space
details: http://hg.videolan.org/x265/rev/e4a7885f377e
branches:
changeset: 5503:e4a7885f377e
user: Steve Borho <steve at borho.org>
date: Wed Dec 04 13:45:29 2013 -0600
description:
encoder: remove trailing white-space
Subject: [x265] cmake: workaround to allow Xcode 5 to link x265 CLI app
details: http://hg.videolan.org/x265/rev/d35b42382331
branches:
changeset: 5504:d35b42382331
user: Steve Borho <steve at borho.org>
date: Wed Dec 04 22:44:18 2013 -0600
description:
cmake: workaround to allow Xcode 5 to link x265 CLI app
diffstat:
source/CMakeLists.txt | 11 +-
source/Lib/TLibCommon/ContextTables.h | 9 +-
source/Lib/TLibEncoder/TEncSbac.cpp | 5 +-
source/VectorClass/README.txt | 1 -
source/VectorClass/instrset.h | 177 -
source/VectorClass/vectorclass.h | 45 -
source/VectorClass/vectori128.h | 5574 ---------------------------------
source/VectorClass/vectori256.h | 4738 ----------------------------
source/VectorClass/vectori256e.h | 3545 --------------------
source/common/CMakeLists.txt | 20 +-
source/common/pixel.cpp | 3 +
source/common/vec/intra-ssse3.cpp | 236 +-
source/common/vec/ipfilter-sse41.cpp | 208 +-
source/common/vec/pixel16-sse41.cpp | 1860 -----------
source/common/vec/vec-primitives.cpp | 7 -
source/common/x86/asm-primitives.cpp | 31 +
source/common/x86/const-a.asm | 6 +
source/common/x86/intrapred.h | 8 +
source/common/x86/intrapred8.asm | 209 +-
source/common/x86/pixel-a.asm | 580 ++-
source/common/x86/pixel-util8.asm | 470 ++-
source/common/x86/sad16-a.asm | 772 ++++
source/encoder/encoder.cpp | 2 +-
source/test/ipfilterharness.cpp | 4 +-
source/test/pixelharness.cpp | 19 +
25 files changed, 1953 insertions(+), 16587 deletions(-)
diffs (truncated from 20037 to 300 lines):
diff -r 55c0bf9d9966 -r d35b42382331 source/CMakeLists.txt
--- a/source/CMakeLists.txt Tue Dec 03 14:14:44 2013 -0600
+++ b/source/CMakeLists.txt Wed Dec 04 22:44:18 2013 -0600
@@ -83,12 +83,6 @@ elseif(CMAKE_COMPILER_IS_GNUCXX)
add_definitions(-mstackrealign)
endif()
execute_process(COMMAND ${CMAKE_CXX_COMPILER} -dumpversion OUTPUT_VARIABLE GCC_VERSION)
- if(NOT GCC_VERSION VERSION_LESS 4.7)
- # this is necessary to avoid name conflicts in vector class
- # library. if vector classes are removed/replaced this can
- # likely be removed as well.
- add_definitions(-fabi-version=6)
- endif()
endif()
if (GCC)
option(WARNINGS_AS_ERRORS "Stop compiles on first warning" OFF)
@@ -258,8 +252,13 @@ if(ENABLE_CLI)
set(GETOPT compat/getopt/getopt.c compat/getopt/getopt.h)
endif(NOT HAVE_GETOPT_H)
+if(XCODE)
+ add_executable(cli ../COPYING ${InputFiles} ${OutputFiles} ${GETOPT} x265.cpp x265.h
+ $<TARGET_OBJECTS:encoder> $<TARGET_OBJECTS:common> ${YASM_OBJS} ${YASM_SRCS})
+else()
add_executable(cli ../COPYING ${InputFiles} ${OutputFiles} ${GETOPT} x265.cpp x265.h)
target_link_libraries(cli x265-static ${PLATFORM_LIBS})
+endif()
set_target_properties(cli PROPERTIES OUTPUT_NAME x265)
install(TARGETS cli DESTINATION bin)
diff -r 55c0bf9d9966 -r d35b42382331 source/Lib/TLibCommon/ContextTables.h
--- a/source/Lib/TLibCommon/ContextTables.h Tue Dec 03 14:14:44 2013 -0600
+++ b/source/Lib/TLibCommon/ContextTables.h Wed Dec 04 22:44:18 2013 -0600
@@ -126,6 +126,9 @@
#define OFF_CU_TRANSQUANT_BYPASS_FLAG_CTX (OFF_TRANSFORMSKIP_FLAG_CTX + 2 * NUM_TRANSFORMSKIP_FLAG_CTX)
#define MAX_OFF_CTX_MOD (OFF_CU_TRANSQUANT_BYPASS_FLAG_CTX + NUM_CU_TRANSQUANT_BYPASS_FLAG_CTX)
+namespace x265 {
+// private namespace
+
// ====================================================================================================================
// Sbac interface
// ====================================================================================================================
@@ -139,8 +142,8 @@ extern const uint8_t g_nextStateMPS[128]
extern const uint8_t g_nextStateLPS[128];
extern const int g_entropyBits[128];
extern uint8_t g_nextState[128][2];
-extern void buildNextStateTable();
-extern uint8_t sbacInit(int qp, int initValue); ///< initialize state with initial probability
+void buildNextStateTable();
+uint8_t sbacInit(int qp, int initValue); ///< initialize state with initial probability
#define sbacGetMps(S) ((S) & 1)
#define sbacGetState(S) ((S) >> 1)
@@ -154,8 +157,6 @@ extern uint8_t sbacInit(int qp, int init
// Tables
// ====================================================================================================================
-namespace x265 {
-// private namespace
// initial probability for cu_transquant_bypass flag
static const uint8_t
diff -r 55c0bf9d9966 -r d35b42382331 source/Lib/TLibEncoder/TEncSbac.cpp
--- a/source/Lib/TLibEncoder/TEncSbac.cpp Tue Dec 03 14:14:44 2013 -0600
+++ b/source/Lib/TLibEncoder/TEncSbac.cpp Wed Dec 04 22:44:18 2013 -0600
@@ -37,7 +37,8 @@
#include "TEncSbac.h"
-using namespace x265;
+namespace x265
+{
//! \ingroup TLibEncoder
//! \{
@@ -2633,4 +2634,6 @@ void TEncSbac::loadContexts(TEncSbac* s
this->xCopyContextsFrom(src);
}
+}
+
//! \}
diff -r 55c0bf9d9966 -r d35b42382331 source/VectorClass/README.txt
--- a/source/VectorClass/README.txt Tue Dec 03 14:14:44 2013 -0600
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1 +0,0 @@
-All the code in this folder originated from http://www.agner.org/optimize/#vectorclass
diff -r 55c0bf9d9966 -r d35b42382331 source/VectorClass/instrset.h
--- a/source/VectorClass/instrset.h Tue Dec 03 14:14:44 2013 -0600
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,177 +0,0 @@
-/**************************** instrset.h **********************************
-| Author: Agner Fog
-| Date created: 2012-05-30
-| Last modified: 2012-08-01
-| Version: 1.02 Beta
-| Project: vector classes
-| Description:
-| Header file for various common tasks to vector class library:
-| > selects the supported instruction set
-| > defines integer types
-| > defines compiler version macro if GCC compiler used
-| > defines template class to represent compile-time integer constant
-| > defines template for compile-time error messages
-|
-| (c) Copyright 2012 GNU General Public License http://www.gnu.org/licenses
-\*****************************************************************************/
-
-#ifndef INSTRSET_H
-#define INSTRSET_H
-
-// Detect 64 bit mode
-#if (defined(_M_AMD64) || defined(_M_X64) || defined(__amd64)) && !defined(__x86_64__)
-#define __x86_64__ 1 // There are many different macros for this, decide on only one
-#endif
-
-// Find instruction set from compiler macros if INSTRSET not defined
-// Note: Not all compilers define these macros automatically
-#ifndef INSTRSET
-#if defined(__AVX2__)
-#define INSTRSET 8
-#elif defined(__AVX__)
-#define INSTRSET 7
-#elif defined(__SSE4_2__)
-#define INSTRSET 6
-#elif defined(__SSE4_1__)
-#define INSTRSET 5
-#elif defined(__SSSE3__)
-#define INSTRSET 4
-#elif defined(__SSE3__)
-#define INSTRSET 3
-#elif defined(__SSE2__) || defined(__x86_64__)
-#define INSTRSET 2
-#elif defined(__SSE__)
-#define INSTRSET 1
-#elif defined(_M_IX86_FP) // Defined in MS compiler. 1: SSE, 2: SSE2
-#define INSTRSET _M_IX86_FP
-#else // if defined(__AVX2__)
-#define INSTRSET 0
-#endif // instruction set defines
-#endif // INSTRSET
-
-// Include the appropriate header file for intrinsic functions
-#if INSTRSET > 7 // AVX2 and later
-#ifdef __GNUC__
-#include <x86intrin.h> // x86intrin.h includes header files for whatever instruction
- // sets are specified on the compiler command line, such as:
- // xopintrin.h, fma4intrin.h
-#else
-#include <immintrin.h> // MS version of immintrin.h covers AVX, AVX2 and FMA3
-#endif // __GNUC__
-#elif INSTRSET == 7
-#include <immintrin.h> // AVX
-#elif INSTRSET == 6
-#include <nmmintrin.h> // SSE4.2
-#elif INSTRSET == 5
-#include <smmintrin.h> // SSE4.1
-#elif INSTRSET == 4
-#include <tmmintrin.h> // SSSE3
-#elif INSTRSET == 3
-#include <pmmintrin.h> // SSE3
-#elif INSTRSET == 2
-#include <emmintrin.h> // SSE2
-#elif INSTRSET == 1
-#include <xmmintrin.h> // SSE
-#endif // INSTRSET
-
-// AMD instruction sets
-#if defined(__XOP__) || defined(__FMA4__)
-#ifdef __GNUC__
-#include <x86intrin.h> // AMD XOP (Gnu)
-#else
-#include <ammintrin.h> // AMD XOP (Microsoft)
-#endif // __GNUC__
-#elif defined(__SSE4A__) // AMD SSE4A
-#include <ammintrin.h>
-#endif // __XOP__
-
-// FMA3 instruction set
-#if defined(__FMA__)
-#include <fmaintrin.h>
-#endif // __FMA__
-
-// FMA4 instruction set
-#if defined(__FMA4__)
-#include <fma4intrin.h> // must have both x86intrin.h and fma4intrin.h, don't know why
-#endif // __FMA4__
-
-// Define integer types with known size
-#if defined(__GNUC__) || (defined(_MSC_VER) && _MSC_VER >= 1600)
-// Compilers supporting C99 or C++0x have stdint.h defining these integer types
-#include <stdint.h>
-#elif defined(_MSC_VER)
-// Older Microsoft compilers have their own definitions
-typedef signed __int8 int8_t;
-typedef unsigned __int8 uint8_t;
-typedef signed __int16 int16_t;
-typedef unsigned __int16 uint16_t;
-typedef signed __int32 int32_t;
-typedef unsigned __int32 uint32_t;
-typedef signed __int64 int64_t;
-typedef unsigned __int64 uint64_t;
-#ifndef _INTPTR_T_DEFINED
-#define _INTPTR_T_DEFINED
-#ifdef __x86_64__
-typedef int64_t intptr_t;
-#else
-typedef int32_t intptr_t;
-#endif
-#endif
-#else // if defined(__GNUC__) || (defined(_MSC_VER) && _MSC_VER >= 1600)
-// This works with most compilers
-typedef signed char int8_t;
-typedef unsigned char uint8_t;
-typedef signed short int int16_t;
-typedef unsigned short int uint16_t;
-typedef signed int int32_t;
-typedef unsigned int uint32_t;
-typedef long long int64_t;
-typedef unsigned long long uint64_t;
-#ifdef __x86_64__
-typedef int64_t intptr_t;
-#else
-typedef int32_t intptr_t;
-#endif
-#endif // if defined(__GNUC__) || (defined(_MSC_VER) && _MSC_VER >= 1600)
-
-#include <cstdlib> // define abs(int)
-
-#ifdef _MSC_VER // Microsoft compiler or compatible Intel compiler
-#include <intrin.h> // define _BitScanReverse(int), __cpuid(int[4],int), _xgetbv(int)
-#endif // _MSC_VER
-
-// GCC version
-#if defined(__GNUC__) && !defined(GCC_VERSION)
-#define GCC_VERSION ((__GNUC__) * 10000 + (__GNUC_MINOR__) * 100 + (__GNUC_PATCHLEVEL__))
-#endif
-
-// Template class to represent compile-time integer constant
-template<int32_t n>
-class Const_int_t
-{}; // represent compile-time signed integer constant
-
-template<uint32_t n>
-class Const_uint_t
-{}; // represent compile-time unsigned integer constant
-
-#define const_int(n) (Const_int_t<n>()) // n must be compile-time integer constant
-#define const_uint(n) (Const_uint_t<n>()) // n must be compile-time unsigned integer constant
-
-// Template for compile-time error messages
-template<bool>
-class Static_error_check
-{
-public:
-
- Static_error_check() {}
-};
-
-template<>
-class Static_error_check<false> // generate compile-time error if false
-{
-private:
-
- Static_error_check() {}
-};
-
-#endif // INSTRSET_H
diff -r 55c0bf9d9966 -r d35b42382331 source/VectorClass/vectorclass.h
--- a/source/VectorClass/vectorclass.h Tue Dec 03 14:14:44 2013 -0600
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,45 +0,0 @@
-/**************************** vectorclass.h ********************************
-* Author: Agner Fog
-* Date created: 2012-05-30
-* Last modified: 2012-08-01
-* Version: 1.02 Beta
-* Project: vector classes
-* Description:
-* Header file defining vector classes as interface to
-* intrinsic functions in x86 microprocessors with SSE2 and later instruction
-* sets up to AVX2.
-*
-* Instructions:
-* Use Gnu, Intel or Microsoft C++ compiler. Compile for the desired
-* instruction set, which must be at least SSE2. Specify the supported
-* instruction set by a command line define, e.g. __SSE4_1__ if the
-* compiler does not automatically do so.
-*
-* Each vector object is represented internally in the CPU as a 128-bit or
-* 256 bit register.
-*
-* This header file includes the appropriate header files depending on the
-* supported instruction set
-*
-* For detailed instructions, see VectorClass.pdf
-*
-* (c) Copyright 2012 GNU General Public License 3.0 http://www.gnu.org/licenses
-******************************************************************************/
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