[x265-commits] [x265] api: improve error handling in x265_api_get() bit depth c...
Steve Borho
steve at borho.org
Tue May 12 20:25:04 CEST 2015
details: http://hg.videolan.org/x265/rev/cfbcac74d1c6
branches: stable
changeset: 10408:cfbcac74d1c6
user: Steve Borho <steve at borho.org>
date: Mon May 11 18:47:37 2015 -0500
description:
api: improve error handling in x265_api_get() bit depth checks
These checks were added to ensure that the returned API supported the bitdepth
that is implied by the library's filename (libx265_main10 should support main10)
but the checks themselves were based on a broken premise. If the file was
misnamed, then it will return NULL if you ask for its implied target bitDepth.
To fix this we always call x265_api_get(0) for the bound library, which must
always return a non-NULL pointer, and then verify that the returned API's bit
depth indeed matches the one implied by its filename.
Subject: [x265] Merge with stable
details: http://hg.videolan.org/x265/rev/f2081ef64fd2
branches:
changeset: 10409:f2081ef64fd2
user: Steve Borho <steve at borho.org>
date: Mon May 11 18:50:03 2015 -0500
description:
Merge with stable
Subject: [x265] asm: filter_vpp, filter_vps for 2x16 in avx2
details: http://hg.videolan.org/x265/rev/fa76d515f068
branches:
changeset: 10410:fa76d515f068
user: Divya Manivannan <divya at multicorewareinc.com>
date: Tue May 12 10:05:04 2015 +0530
description:
asm: filter_vpp, filter_vps for 2x16 in avx2
filter_vpp[2x16]: 859c->528c
filter_vps[2x16]: 724c->452c
Subject: [x265] asm: avx2 code for sad[32x64] for 10 bpp(6222 -> 2427)
details: http://hg.videolan.org/x265/rev/f7bfa7137527
branches:
changeset: 10411:f7bfa7137527
user: Sumalatha Polureddy
date: Tue May 12 11:45:38 2015 +0530
description:
asm: avx2 code for sad[32x64] for 10 bpp(6222 -> 2427)
sse2
sad[32x64] 2.82x 6222.04 17557.96
avx2
sad[32x64] 7.05x 2427.57 17121.56
Subject: [x265] asm: intra_pred_dc32 high_bit_depth code
details: http://hg.videolan.org/x265/rev/92c376797aab
branches:
changeset: 10412:92c376797aab
user: Dnyaneshwar G <dnyaneshwar at multicorewareinc.com>
date: Tue May 12 11:04:20 2015 +0530
description:
asm: intra_pred_dc32 high_bit_depth code
AVX2:
intra_dc_32x32 19.36x 780.92 15118.54
SSE:
intra_dc_32x32 10.41x 1457.15 15167.84
Subject: [x265] asm: avx2 code for high_bit_depth intra_dc_16x16
details: http://hg.videolan.org/x265/rev/4c3e5de1ef92
branches:
changeset: 10413:4c3e5de1ef92
user: Dnyaneshwar G <dnyaneshwar at multicorewareinc.com>
date: Tue May 12 11:07:51 2015 +0530
description:
asm: avx2 code for high_bit_depth intra_dc_16x16
AVX2:
intra_dc_16x16[filter=0] 18.78x 231.65 4350.17
intra_dc_16x16[filter=1] 10.76x 467.37 5028.99
SSE:
intra_dc_16x16[filter=0] 9.46x 459.22 4345.05
intra_dc_16x16[filter=1] 7.19x 692.54 4976.13
Subject: [x265] asm: avx2 code for high_bit_depth intra_planar_16x16
details: http://hg.videolan.org/x265/rev/b2d0724cd414
branches:
changeset: 10414:b2d0724cd414
user: Dnyaneshwar G <dnyaneshwar at multicorewareinc.com>
date: Mon May 11 11:07:10 2015 +0530
description:
asm: avx2 code for high_bit_depth intra_planar_16x16
AVX2:
intra_planar_16x16 19.84x 478.04 9483.19
SSE:
intra_planar_16x16 12.91x 793.82 10248.45
Subject: [x265] asm: avx2 code for high_bit_depth intra_pred_planar32x32
details: http://hg.videolan.org/x265/rev/e5790f025252
branches:
changeset: 10415:e5790f025252
user: Dnyaneshwar G <dnyaneshwar at multicorewareinc.com>
date: Tue May 12 11:13:47 2015 +0530
description:
asm: avx2 code for high_bit_depth intra_pred_planar32x32
AVX2:
intra_planar_32x32 28.16x 1532.45 43154.74
SSE:
intra_planar_32x32 4.42x 10169.50 44932.19
Subject: [x265] asm: avx2 code for high_bit_depth psyCost_pp_4x4, reduced 400c->250c
details: http://hg.videolan.org/x265/rev/571f66f7bc92
branches:
changeset: 10416:571f66f7bc92
user: Dnyaneshwar G <dnyaneshwar at multicorewareinc.com>
date: Mon May 11 17:16:49 2015 +0530
description:
asm: avx2 code for high_bit_depth psyCost_pp_4x4, reduced 400c->250c
Subject: [x265] asm: enable psyCost_ss avx2 for HIGH_BIT_DEPTH
details: http://hg.videolan.org/x265/rev/132bbcbdfdd6
branches:
changeset: 10417:132bbcbdfdd6
user: Dnyaneshwar G <dnyaneshwar at multicorewareinc.com>
date: Tue May 12 12:04:05 2015 +0530
description:
asm: enable psyCost_ss avx2 for HIGH_BIT_DEPTH
Subject: [x265] improve codeCoeffNxN by bypass check on one coeff block
details: http://hg.videolan.org/x265/rev/0c25c97667d0
branches:
changeset: 10418:0c25c97667d0
user: Min Chen <chenm003 at 163.com>
date: Mon May 11 16:25:39 2015 -0700
description:
improve codeCoeffNxN by bypass check on one coeff block
Subject: [x265] convert for_loop to do_while in codeCoeffNxN(), because all of scanPosSigOff positive now
details: http://hg.videolan.org/x265/rev/dea13c27244c
branches:
changeset: 10419:dea13c27244c
user: Min Chen <chenm003 at 163.com>
date: Mon May 11 16:25:42 2015 -0700
description:
convert for_loop to do_while in codeCoeffNxN(), because all of scanPosSigOff positive now
Subject: [x265] convert for_loop to do_while in codeCoeffNxN(), because all of count are positive
details: http://hg.videolan.org/x265/rev/3e977f460897
branches:
changeset: 10420:3e977f460897
user: Min Chen <chenm003 at 163.com>
date: Mon May 11 16:25:45 2015 -0700
description:
convert for_loop to do_while in codeCoeffNxN(), because all of count are positive
Subject: [x265] reduce conditional operators on c1Flag loop in codeCoeffNxN()
details: http://hg.videolan.org/x265/rev/f5b5cc7fc4f9
branches:
changeset: 10421:f5b5cc7fc4f9
user: Min Chen <chenm003 at 163.com>
date: Mon May 11 16:25:48 2015 -0700
description:
reduce conditional operators on c1Flag loop in codeCoeffNxN()
Subject: [x265] reduce shift operators in cost on coeffRemain
details: http://hg.videolan.org/x265/rev/d81a4f4e7556
branches:
changeset: 10422:d81a4f4e7556
user: Min Chen <chenm003 at 163.com>
date: Mon May 11 16:25:51 2015 -0700
description:
reduce shift operators in cost on coeffRemain
Subject: [x265] asm: interp_4tap_vert_pp sse2
details: http://hg.videolan.org/x265/rev/72f69b308b55
branches:
changeset: 10423:72f69b308b55
user: David T Yuen <dtyx265 at gmail.com>
date: Mon May 11 18:13:13 2015 -0700
description:
asm: interp_4tap_vert_pp sse2
This replaces c code for 12x16 and 12x32
64-bit
./test/TestBench --testbench interp | grep vpp | grep "\[12x"
chroma_vpp[12x16] 2.84x 8530.57 24230.43
chroma_vpp[12x32] 2.83x 16971.29 48070.71
chroma_vpp[12x16] 2.83x 8554.99 24231.62
Subject: [x265] asm: interp_4tap_vert_pp sse2
details: http://hg.videolan.org/x265/rev/d7c824703b1c
branches:
changeset: 10424:d7c824703b1c
user: David T Yuen <dtyx265 at gmail.com>
date: Mon May 11 18:27:53 2015 -0700
description:
asm: interp_4tap_vert_pp sse2
This replaces c code for 16x4, 16x8, 16x12, 16x16, 16x24, 16x32 and 16x64
64-bit
./test/TestBench --testbench interp | grep vpp | grep "\[16x"
chroma_vpp[16x16] 3.88x 8315.81 32231.19
chroma_vpp[16x32] 3.86x 16655.79 64253.14
chroma_vpp[16x12] 3.92x 6195.00 24270.74
chroma_vpp[16x32] 3.80x 16904.33 64266.04
chroma_vpp[16x16] 3.80x 8474.99 32229.99
chroma_vpp[16x64] 3.89x 32941.52 128126.67
chroma_vpp[16x24] 3.85x 12545.20 48342.41
chroma_vpp[16x16] 3.80x 8474.99 32237.87
chroma_vpp[16x32] 3.84x 16755.88 64299.57
chroma_vpp[16x12] 3.81x 6375.01 24271.03
chroma_vpp[16x64] 3.79x 33797.51 127963.79
Subject: [x265] asm: interp_4tap_vert_pp sse2
details: http://hg.videolan.org/x265/rev/c45c2b9a626a
branches:
changeset: 10425:c45c2b9a626a
user: David T Yuen <dtyx265 at gmail.com>
date: Mon May 11 18:39:29 2015 -0700
description:
asm: interp_4tap_vert_pp sse2
This replaces c code for 24x32 and 24x64
64_bit
./test/TestBench --testbench interp | grep vpp | grep "\[24x"
chroma_vpp[24x32] 7.41x 24623.48 182517.88
chroma_vpp[24x64] 7.39x 49337.02 364733.53
chroma_vpp[24x32] 7.41x 24622.11 182386.27
Subject: [x265] cli: we can no longer use compiled bit-depth for dither
details: http://hg.videolan.org/x265/rev/37abdd8805b1
branches: stable
changeset: 10426:37abdd8805b1
user: Steve Borho <steve at borho.org>
date: Tue May 12 09:56:50 2015 -0500
description:
cli: we can no longer use compiled bit-depth for dither
Now that the CLI can use a libx265 with a different bit depth than what it was
compiled against, dither logic needs to use param->internalBitDepth.
Subject: [x265] Merge with stable
details: http://hg.videolan.org/x265/rev/bcd87294cf40
branches:
changeset: 10427:bcd87294cf40
user: Steve Borho <steve at borho.org>
date: Tue May 12 09:57:50 2015 -0500
description:
Merge with stable
Subject: [x265] entropy: fix build warning in checked GCC builds
details: http://hg.videolan.org/x265/rev/6a8b7e352136
branches:
changeset: 10428:6a8b7e352136
user: Steve Borho <steve at borho.org>
date: Tue May 12 10:45:38 2015 -0500
description:
entropy: fix build warning in checked GCC builds
c1 is unsigned, so checking >= 0 is redundant
diffstat:
source/common/x86/asm-primitives.cpp | 44 +
source/common/x86/const-a.asm | 2 +-
source/common/x86/intrapred.h | 1 +
source/common/x86/intrapred16.asm | 327 ++++++++++++
source/common/x86/ipfilter8.asm | 926 +++++++++++++++++++++++++---------
source/common/x86/ipfilter8.h | 11 +
source/common/x86/pixel-a.asm | 71 ++
source/common/x86/sad16-a.asm | 371 ++++++++++++++
source/encoder/api.cpp | 28 +-
source/encoder/entropy.cpp | 74 +-
source/x265.cpp | 6 +-
11 files changed, 1572 insertions(+), 289 deletions(-)
diffs (truncated from 2235 to 300 lines):
diff -r dadd6c419e55 -r 6a8b7e352136 source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Mon May 11 08:50:41 2015 -0500
+++ b/source/common/x86/asm-primitives.cpp Tue May 12 10:45:38 2015 -0500
@@ -1181,6 +1181,20 @@ void setupAssemblyPrimitives(EncoderPrim
}
if (cpuMask & X265_CPU_AVX2)
{
+ p.cu[BLOCK_4x4].psy_cost_ss = x265_psyCost_ss_4x4_avx2;
+ p.cu[BLOCK_8x8].psy_cost_ss = x265_psyCost_ss_8x8_avx2;
+ p.cu[BLOCK_16x16].psy_cost_ss = x265_psyCost_ss_16x16_avx2;
+ p.cu[BLOCK_32x32].psy_cost_ss = x265_psyCost_ss_32x32_avx2;
+ p.cu[BLOCK_64x64].psy_cost_ss = x265_psyCost_ss_64x64_avx2;
+
+ p.cu[BLOCK_4x4].psy_cost_pp = x265_psyCost_pp_4x4_avx2;
+
+ p.cu[BLOCK_16x16].intra_pred[PLANAR_IDX] = x265_intra_pred_planar16_avx2;
+ p.cu[BLOCK_32x32].intra_pred[PLANAR_IDX] = x265_intra_pred_planar32_avx2;
+
+ p.cu[BLOCK_16x16].intra_pred[DC_IDX] = x265_intra_pred_dc16_avx2;
+ p.cu[BLOCK_32x32].intra_pred[DC_IDX] = x265_intra_pred_dc32_avx2;
+
p.pu[LUMA_48x64].satd = x265_pixel_satd_48x64_avx2;
p.pu[LUMA_64x16].satd = x265_pixel_satd_64x16_avx2;
@@ -1264,6 +1278,12 @@ void setupAssemblyPrimitives(EncoderPrim
p.pu[LUMA_16x12].sad = x265_pixel_sad_16x12_avx2;
p.pu[LUMA_16x16].sad = x265_pixel_sad_16x16_avx2;
p.pu[LUMA_16x32].sad = x265_pixel_sad_16x32_avx2;
+ p.pu[LUMA_16x64].sad = x265_pixel_sad_16x64_avx2;
+ p.pu[LUMA_32x8].sad = x265_pixel_sad_32x8_avx2;
+ p.pu[LUMA_32x16].sad = x265_pixel_sad_32x16_avx2;
+ p.pu[LUMA_32x24].sad = x265_pixel_sad_32x24_avx2;
+ p.pu[LUMA_32x32].sad = x265_pixel_sad_32x32_avx2;
+ p.pu[LUMA_32x64].sad = x265_pixel_sad_32x64_avx2;
p.pu[LUMA_16x4].convert_p2s = x265_filterPixelToShort_16x4_avx2;
p.pu[LUMA_16x8].convert_p2s = x265_filterPixelToShort_16x8_avx2;
@@ -1392,6 +1412,13 @@ void setupAssemblyPrimitives(EncoderPrim
p.chroma[X265_CSP_I420].pu[CHROMA_420_8x8].filter_vpp = x265_interp_4tap_vert_pp_8x8_sse2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_8x16].filter_vpp = x265_interp_4tap_vert_pp_8x16_sse2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_8x32].filter_vpp = x265_interp_4tap_vert_pp_8x32_sse2;
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_12x16].filter_vpp = x265_interp_4tap_vert_pp_12x16_sse2;
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_16x4].filter_vpp = x265_interp_4tap_vert_pp_16x4_sse2;
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_16x8].filter_vpp = x265_interp_4tap_vert_pp_16x8_sse2;
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_16x12].filter_vpp = x265_interp_4tap_vert_pp_16x12_sse2;
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_16x16].filter_vpp = x265_interp_4tap_vert_pp_16x16_sse2;
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_16x32].filter_vpp = x265_interp_4tap_vert_pp_16x32_sse2;
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_24x32].filter_vpp = x265_interp_4tap_vert_pp_24x32_sse2;
p.chroma[X265_CSP_I422].pu[CHROMA_422_6x16].filter_vpp = x265_interp_4tap_vert_pp_6x16_sse2;
p.chroma[X265_CSP_I422].pu[CHROMA_422_8x4].filter_vpp = x265_interp_4tap_vert_pp_8x4_sse2;
p.chroma[X265_CSP_I422].pu[CHROMA_422_8x4].filter_vpp = x265_interp_4tap_vert_pp_8x4_sse2;
@@ -1400,10 +1427,25 @@ void setupAssemblyPrimitives(EncoderPrim
p.chroma[X265_CSP_I422].pu[CHROMA_422_8x16].filter_vpp = x265_interp_4tap_vert_pp_8x16_sse2;
p.chroma[X265_CSP_I422].pu[CHROMA_422_8x32].filter_vpp = x265_interp_4tap_vert_pp_8x32_sse2;
p.chroma[X265_CSP_I422].pu[CHROMA_422_8x64].filter_vpp = x265_interp_4tap_vert_pp_8x64_sse2;
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_12x32].filter_vpp = x265_interp_4tap_vert_pp_12x32_sse2;
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_16x8].filter_vpp = x265_interp_4tap_vert_pp_16x8_sse2;
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_16x16].filter_vpp = x265_interp_4tap_vert_pp_16x16_sse2;
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_16x24].filter_vpp = x265_interp_4tap_vert_pp_16x24_sse2;
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_16x32].filter_vpp = x265_interp_4tap_vert_pp_16x32_sse2;
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_16x64].filter_vpp = x265_interp_4tap_vert_pp_16x64_sse2;
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_24x64].filter_vpp = x265_interp_4tap_vert_pp_24x64_sse2;
p.chroma[X265_CSP_I444].pu[LUMA_8x4].filter_vpp = x265_interp_4tap_vert_pp_8x4_sse2;
p.chroma[X265_CSP_I444].pu[LUMA_8x8].filter_vpp = x265_interp_4tap_vert_pp_8x8_sse2;
p.chroma[X265_CSP_I444].pu[LUMA_8x16].filter_vpp = x265_interp_4tap_vert_pp_8x16_sse2;
p.chroma[X265_CSP_I444].pu[LUMA_8x32].filter_vpp = x265_interp_4tap_vert_pp_8x32_sse2;
+ p.chroma[X265_CSP_I444].pu[LUMA_12x16].filter_vpp = x265_interp_4tap_vert_pp_12x16_sse2;
+ p.chroma[X265_CSP_I444].pu[LUMA_16x4].filter_vpp = x265_interp_4tap_vert_pp_16x4_sse2;
+ p.chroma[X265_CSP_I444].pu[LUMA_16x8].filter_vpp = x265_interp_4tap_vert_pp_16x8_sse2;
+ p.chroma[X265_CSP_I444].pu[LUMA_16x12].filter_vpp = x265_interp_4tap_vert_pp_16x12_sse2;
+ p.chroma[X265_CSP_I444].pu[LUMA_16x16].filter_vpp = x265_interp_4tap_vert_pp_16x16_sse2;
+ p.chroma[X265_CSP_I444].pu[LUMA_16x32].filter_vpp = x265_interp_4tap_vert_pp_16x32_sse2;
+ p.chroma[X265_CSP_I444].pu[LUMA_16x64].filter_vpp = x265_interp_4tap_vert_pp_16x64_sse2;
+ p.chroma[X265_CSP_I444].pu[LUMA_24x32].filter_vpp = x265_interp_4tap_vert_pp_24x32_sse2;
#endif
ALL_LUMA_PU(luma_hpp, interp_8tap_horiz_pp, sse2);
@@ -2617,6 +2659,7 @@ void setupAssemblyPrimitives(EncoderPrim
p.chroma[X265_CSP_I422].pu[CHROMA_422_8x12].filter_vps = x265_interp_4tap_vert_ps_8x12_avx2;
p.chroma[X265_CSP_I422].pu[CHROMA_422_2x4].filter_vps = x265_interp_4tap_vert_ps_2x4_avx2;
p.chroma[X265_CSP_I422].pu[CHROMA_422_16x24].filter_vps = x265_interp_4tap_vert_ps_16x24_avx2;
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_2x16].filter_vps = x265_interp_4tap_vert_ps_2x16_avx2;
//i444 for chroma_vps
p.chroma[X265_CSP_I444].pu[LUMA_4x4].filter_vps = x265_interp_4tap_vert_ps_4x4_avx2;
@@ -2662,6 +2705,7 @@ void setupAssemblyPrimitives(EncoderPrim
p.chroma[X265_CSP_I422].pu[CHROMA_422_8x12].filter_vpp = x265_interp_4tap_vert_pp_8x12_avx2;
p.chroma[X265_CSP_I422].pu[CHROMA_422_2x4].filter_vpp = x265_interp_4tap_vert_pp_2x4_avx2;
p.chroma[X265_CSP_I422].pu[CHROMA_422_16x24].filter_vpp = x265_interp_4tap_vert_pp_16x24_avx2;
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_2x16].filter_vpp = x265_interp_4tap_vert_pp_2x16_avx2;
//i444 for chroma_vpp
p.chroma[X265_CSP_I444].pu[LUMA_4x4].filter_vpp = x265_interp_4tap_vert_pp_4x4_avx2;
diff -r dadd6c419e55 -r 6a8b7e352136 source/common/x86/const-a.asm
--- a/source/common/x86/const-a.asm Mon May 11 08:50:41 2015 -0500
+++ b/source/common/x86/const-a.asm Tue May 12 10:45:38 2015 -0500
@@ -62,7 +62,7 @@ const pb_000000000000000F, db
;; 16-bit constants
const pw_1, times 16 dw 1
-const pw_2, times 8 dw 2
+const pw_2, times 16 dw 2
const pw_m2, times 8 dw -2
const pw_4, times 8 dw 4
const pw_8, times 8 dw 8
diff -r dadd6c419e55 -r 6a8b7e352136 source/common/x86/intrapred.h
--- a/source/common/x86/intrapred.h Mon May 11 08:50:41 2015 -0500
+++ b/source/common/x86/intrapred.h Tue May 12 10:45:38 2015 -0500
@@ -34,6 +34,7 @@ void x265_intra_pred_dc4_sse4(pixel* dst
void x265_intra_pred_dc8_sse4(pixel* dst, intptr_t dstStride, const pixel* srcPix, int, int filter);
void x265_intra_pred_dc16_sse4(pixel* dst, intptr_t dstStride, const pixel* srcPix, int, int filter);
void x265_intra_pred_dc32_sse4(pixel* dst, intptr_t dstStride, const pixel* srcPix, int, int filter);
+void x265_intra_pred_dc16_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int, int filter);
void x265_intra_pred_dc32_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int, int filter);
void x265_intra_pred_planar4_sse2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int, int);
diff -r dadd6c419e55 -r 6a8b7e352136 source/common/x86/intrapred16.asm
--- a/source/common/x86/intrapred16.asm Mon May 11 08:50:41 2015 -0500
+++ b/source/common/x86/intrapred16.asm Tue May 12 10:45:38 2015 -0500
@@ -89,7 +89,9 @@ cextern pw_1
cextern pw_2
cextern pw_4
cextern pw_8
+cextern pw_15
cextern pw_16
+cextern pw_31
cextern pw_32
cextern pw_1023
cextern pd_16
@@ -103,6 +105,8 @@ cextern multi_2Row
cextern pw_swap
cextern pb_unpackwq1
cextern pb_unpackwq2
+cextern pw_planar16_mul
+cextern pw_planar32_mul
;-----------------------------------------------------------------------------------
; void intra_pred_dc(pixel* dst, intptr_t dstStride, pixel* above, int, int filter)
@@ -448,6 +452,218 @@ cglobal intra_pred_dc32, 3, 4, 6
%endrep
RET
+;-------------------------------------------------------------------------------------------------------
+; void intra_pred_dc(pixel* dst, intptr_t dstStride, pixel* left, pixel* above, int dirMode, int filter)
+;-------------------------------------------------------------------------------------------------------
+INIT_YMM avx2
+cglobal intra_pred_dc16, 3, 9, 4
+ mov r3d, r4m
+ add r1d, r1d
+ movu m0, [r2 + 66]
+ movu m2, [r2 + 2]
+ paddw m0, m2
+
+ vextracti128 xm1, m0, 1
+ paddw xm0, xm1
+ movhlps xm1, xm0
+ paddw xm0, xm1
+ phaddw xm0, xm0
+ pmaddwd xm0, [pw_1]
+ paddd xm0, [pd_16]
+ psrad xm0, 5
+ movd r5d, xm0
+ vpbroadcastw m0, xm0
+
+ test r3d, r3d
+
+ ; store DC 16x16
+ lea r6, [r1 + r1 * 2] ; index 3
+ lea r7, [r1 + r1 * 4] ; index 5
+ lea r8, [r6 + r1 * 4] ; index 7
+ lea r4, [r0 + r8 * 1] ; base + 7
+
+ movu [r0], m0
+ movu [r0 + r1], m0
+ movu [r0 + r1 * 2], m0
+ movu [r0 + r6], m0
+ movu [r0 + r1 * 4], m0
+ movu [r0 + r7], m0
+ movu [r0 + r6 * 2], m0
+ movu [r4], m0
+ movu [r0 + r1 * 8], m0
+ movu [r4 + r1 * 2], m0
+ movu [r0 + r7 * 2], m0
+ movu [r4 + r1 * 4], m0
+ movu [r0 + r6 * 4], m0
+ movu [r4 + r6 * 2], m0
+ movu [r4 + r8], m0
+ movu [r4 + r1 * 8], m0
+
+ ; Do DC Filter
+ jz .end
+ mova m1, [pw_2]
+ pmullw m1, m0
+ paddw m1, [pw_2]
+ movd r3d, xm1
+ paddw m1, m0
+
+ ; filter top
+ movu m2, [r2 + 2]
+ paddw m2, m1
+ psraw m2, 2
+ movu [r0], m2
+
+ ; filter top-left
+ movzx r3d, r3w
+ movzx r5d, word [r2 + 66]
+ add r3d, r5d
+ movzx r5d, word [r2 + 2]
+ add r5d, r3d
+ shr r5d, 2
+ mov [r0], r5w
+
+ ; filter left
+ movu m2, [r2 + 68]
+ paddw m2, m1
+ psraw m2, 2
+ vextracti128 xm3, m2, 1
+
+ movq r3, xm2
+ pshufd xm2, xm2, 0xEE
+ mov [r0 + r1], r3w
+ shr r3, 16
+ mov [r0 + r1 * 2], r3w
+ shr r3, 16
+ mov [r0 + r6], r3w
+ shr r3, 16
+ mov [r0 + r1 * 4], r3w
+ movq r3, xm2
+ mov [r0 + r7], r3w
+ shr r3, 16
+ mov [r0 + r6 * 2], r3w
+ shr r3, 16
+ mov [r4], r3w
+ shr r3, 16
+ mov [r0 + r1 * 8], r3w
+
+ movq r3, xm3
+ pshufd xm3, xm3, 0xEE
+ mov [r4 + r1 * 2], r3w
+ shr r3, 16
+ mov [r0 + r7 * 2], r3w
+ shr r3, 16
+ mov [r4 + r1 * 4], r3w
+ shr r3, 16
+ mov [r0 + r6 * 4], r3w
+ movq r3, xm3
+ mov [r4 + r6 * 2], r3w
+ shr r3, 16
+ mov [r4 + r8], r3w
+ shr r3, 16
+ mov [r4 + r1 * 8], r3w
+.end:
+ RET
+
+;---------------------------------------------------------------------------------------------
+; void intra_pred_dc(pixel* dst, intptr_t dstStride, pixel *srcPix, int dirMode, int bFilter)
+;---------------------------------------------------------------------------------------------
+INIT_YMM avx2
+cglobal intra_pred_dc32, 3, 3, 2
+ add r2, 2
+ add r1d, r1d
+ movu m0, [r2]
+ movu m1, [r2 + 32]
+ add r2, mmsize*4 ; r2 += 128
+ paddw m0, m1
+ movu m1, [r2]
+ paddw m0, m1
+ movu m1, [r2 + 32]
+ paddw m0, m1
+ vextracti128 xm1, m0, 1
+ paddw xm0, xm1
+ movhlps xm1, xm0
+ paddw xm0, xm1
+ phaddw xm0, xm0
+ pmaddwd xm0, [pw_1]
+ paddd xm0, [pd_32] ; sum = sum + 32
+ psrld xm0, 6 ; sum = sum / 64
+ vpbroadcastw m0, xm0
+
+ lea r2, [r1 * 3]
+ ; store DC 32x32
+ movu [r0 + r1 * 0 + 0], m0
+ movu [r0 + r1 * 0 + mmsize], m0
+ movu [r0 + r1 * 1 + 0], m0
+ movu [r0 + r1 * 1 + mmsize], m0
+ movu [r0 + r1 * 2 + 0], m0
+ movu [r0 + r1 * 2 + mmsize], m0
+ movu [r0 + r2 * 1 + 0], m0
+ movu [r0 + r2 * 1 + mmsize], m0
+ lea r0, [r0 + r1 * 4]
+ movu [r0 + r1 * 0 + 0], m0
+ movu [r0 + r1 * 0 + mmsize], m0
+ movu [r0 + r1 * 1 + 0], m0
+ movu [r0 + r1 * 1 + mmsize], m0
+ movu [r0 + r1 * 2 + 0], m0
+ movu [r0 + r1 * 2 + mmsize], m0
+ movu [r0 + r2 * 1 + 0], m0
+ movu [r0 + r2 * 1 + mmsize], m0
+ lea r0, [r0 + r1 * 4]
+ movu [r0 + r1 * 0 + 0], m0
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