[x264-devel] [PATCH] MIPS MSA checkasm updated

[Rishikesh More]

Indeed. I am resubmitting patch with proper instruction.

- Rishikesh

-----Original Message-----
From: x264-devel [mailto:x264-devel-bounces at videolan.org] On Behalf Of Henrik Gramner
Sent: Friday, May 8, 2015 9:21 PM
To: Mailing list for x264 developers
Subject: Re: [x264-devel] [PATCH] MIPS MSA checkasm updated

> +    asm volatile( "move.v $w5, $w11" : "=r"(a) :: "memory" );

My MIPS knowledge is quite limited, but this doesn't look correct.
Isn't the cycle counter located in coprocessor 0 register 9, e.g.
wouldn't "mfc0 %0, $9" be the correct instruction?
_______________________________________________
x264-devel mailing list
x264-devel at videolan.org
https://mailman.videolan.org/listinfo/x264-devel