[x265] [PATCH] pixel8.inc: sad_x3_4 integrated faster MMX code for 32-bit build
Steve Borho
steve at borho.org
Mon Aug 26 01:50:52 CEST 2013
On Sun, Aug 25, 2013 at 12:16 AM, <praveen at multicorewareinc.com> wrote:
> # HG changeset patch
> # User praveentiwari
> # Date 1377407801 -19800
> # Node ID 2d9f2ffb4b5da6e1a1f5a156ee26c2747161a749
> # Parent 5e31b5b7fbe5c908d4545d4db526aebca16d0fa2
> pixel8.inc: sad_x3_4 integrated faster MMX code for 32-bit build
>
I've pushed all these changes, it seems you've been busy this weekend. I
have one request (see below)
> diff -r 5e31b5b7fbe5 -r 2d9f2ffb4b5d source/common/vec/pixel8.inc
> --- a/source/common/vec/pixel8.inc Sun Aug 25 10:37:56 2013 +0530
> +++ b/source/common/vec/pixel8.inc Sun Aug 25 10:46:41 2013 +0530
> @@ -1316,6 +1316,7 @@
> }
>
> #if INSTRSET >= X265_CPU_LEVEL_SSE41
>
> +#ifdef X86_64
>
Since other compilers seem to be able to generate MMX intrinsics just fine,
it is somewhat unfair to disable MMX versions for all 64bit compiles.
Please add a define at the top of this file named HAVE_MMX and have it
evaluate to true for every compiler except the ones we know are broken
(MSVC x64), and then use this macro instead of X86_64.
> template<int ly>
> void sad_x3_4(pixel *fenc, pixel *fref1, pixel *fref2, pixel *fref3,
> intptr_t frefstride, int *res)
> {
> @@ -1821,6 +1822,368 @@
> }
> }
>
> +#else /* ifdef X86_64 */
> +template<int ly>
> +void sad_x3_4(pixel *fenc, pixel *fref1, pixel *fref2, pixel *fref3,
> intptr_t frefstride, int *res)
> +{
> + assert((ly % 4) == 0);
> +
> + __m64 sum0 = _mm_setzero_si64();
> + __m64 sum1 = _mm_setzero_si64();
> + __m64 sum2 = _mm_setzero_si64();
> +
> + __m64 T00, T01, T02, T03, T04, T05, T06, T07;
> + __m64 T0, T1, T2, T3, T4, T5, T6, T7;
> + __m64 T10, T11, T12, T13, T14, T15, T16, T17;
> + __m64 T20, T21, T22, T23, T24, T25, T26, T27;
> +
> + if ((ly % 16) == 0)
> + {
> + for (int i = 0; i < ly; i += 16)
> + {
> + T00 = _mm_cvtsi32_si64(*(int*)(fenc + (i + 0) * FENC_STRIDE));
> + T01 = _mm_cvtsi32_si64(*(int*)(fenc + (i + 1) * FENC_STRIDE));
> + T02 = _mm_cvtsi32_si64(*(int*)(fenc + (i + 2) * FENC_STRIDE));
> + T03 = _mm_cvtsi32_si64(*(int*)(fenc + (i + 3) * FENC_STRIDE));
> + T04 = _mm_cvtsi32_si64(*(int*)(fenc + (i + 4) * FENC_STRIDE));
> + T05 = _mm_cvtsi32_si64(*(int*)(fenc + (i + 5) * FENC_STRIDE));
> + T06 = _mm_cvtsi32_si64(*(int*)(fenc + (i + 6) * FENC_STRIDE));
> + T07 = _mm_cvtsi32_si64(*(int*)(fenc + (i + 7) * FENC_STRIDE));
> + T0 = _mm_cvtsi32_si64(*(int*)(fenc + (i + 8) * FENC_STRIDE));
> + T1 = _mm_cvtsi32_si64(*(int*)(fenc + (i + 9) * FENC_STRIDE));
> + T2 = _mm_cvtsi32_si64(*(int*)(fenc + (i + 10) * FENC_STRIDE));
> + T3 = _mm_cvtsi32_si64(*(int*)(fenc + (i + 11) * FENC_STRIDE));
> + T4 = _mm_cvtsi32_si64(*(int*)(fenc + (i + 12) * FENC_STRIDE));
> + T5 = _mm_cvtsi32_si64(*(int*)(fenc + (i + 13) * FENC_STRIDE));
> + T6 = _mm_cvtsi32_si64(*(int*)(fenc + (i + 14) * FENC_STRIDE));
> + T7 = _mm_cvtsi32_si64(*(int*)(fenc + (i + 15) * FENC_STRIDE));
> +
> + T10 = _mm_cvtsi32_si64(*(int*)(fref1 + (i + 0) * frefstride));
> + T11 = _mm_cvtsi32_si64(*(int*)(fref1 + (i + 1) * frefstride));
> + T12 = _mm_cvtsi32_si64(*(int*)(fref1 + (i + 2) * frefstride));
> + T13 = _mm_cvtsi32_si64(*(int*)(fref1 + (i + 3) * frefstride));
> + T14 = _mm_cvtsi32_si64(*(int*)(fref1 + (i + 4) * frefstride));
> + T15 = _mm_cvtsi32_si64(*(int*)(fref1 + (i + 5) * frefstride));
> + T16 = _mm_cvtsi32_si64(*(int*)(fref1 + (i + 6) * frefstride));
> + T17 = _mm_cvtsi32_si64(*(int*)(fref1 + (i + 7) * frefstride));
> +
> + T20 = _mm_sad_pu8(T00, T10);
> + T21 = _mm_sad_pu8(T01, T11);
> + T22 = _mm_sad_pu8(T02, T12);
> + T23 = _mm_sad_pu8(T03, T13);
> + T24 = _mm_sad_pu8(T04, T14);
> + T25 = _mm_sad_pu8(T05, T15);
> + T26 = _mm_sad_pu8(T06, T16);
> + T27 = _mm_sad_pu8(T07, T17);
> +
> + sum0 = _mm_add_pi16(sum0, T20);
> + sum0 = _mm_add_pi16(sum0, T21);
> + sum0 = _mm_add_pi16(sum0, T22);
> + sum0 = _mm_add_pi16(sum0, T23);
> + sum0 = _mm_add_pi16(sum0, T24);
> + sum0 = _mm_add_pi16(sum0, T25);
> + sum0 = _mm_add_pi16(sum0, T26);
> + sum0 = _mm_add_pi16(sum0, T27);
> +
> + T10 = _mm_cvtsi32_si64(*(int*)(fref1 + (i + 8) * frefstride));
> + T11 = _mm_cvtsi32_si64(*(int*)(fref1 + (i + 9) * frefstride));
> + T12 = _mm_cvtsi32_si64(*(int*)(fref1 + (i + 10) *
> frefstride));
> + T13 = _mm_cvtsi32_si64(*(int*)(fref1 + (i + 11) *
> frefstride));
> + T14 = _mm_cvtsi32_si64(*(int*)(fref1 + (i + 12) *
> frefstride));
> + T15 = _mm_cvtsi32_si64(*(int*)(fref1 + (i + 13) *
> frefstride));
> + T16 = _mm_cvtsi32_si64(*(int*)(fref1 + (i + 14) *
> frefstride));
> + T17 = _mm_cvtsi32_si64(*(int*)(fref1 + (i + 15) *
> frefstride));
> +
> + T20 = _mm_sad_pu8(T0, T10);
> + T21 = _mm_sad_pu8(T1, T11);
> + T22 = _mm_sad_pu8(T2, T12);
> + T23 = _mm_sad_pu8(T3, T13);
> + T24 = _mm_sad_pu8(T4, T14);
> + T25 = _mm_sad_pu8(T5, T15);
> + T26 = _mm_sad_pu8(T6, T16);
> + T27 = _mm_sad_pu8(T7, T17);
> +
> + sum0 = _mm_add_pi16(sum0, T20);
> + sum0 = _mm_add_pi16(sum0, T21);
> + sum0 = _mm_add_pi16(sum0, T22);
> + sum0 = _mm_add_pi16(sum0, T23);
> + sum0 = _mm_add_pi16(sum0, T24);
> + sum0 = _mm_add_pi16(sum0, T25);
> + sum0 = _mm_add_pi16(sum0, T26);
> + sum0 = _mm_add_pi16(sum0, T27);
> + res[0] = _m_to_int(sum0);
> +
> + T10 = _mm_cvtsi32_si64(*(int*)(fref2 + (i + 0) * frefstride));
> + T11 = _mm_cvtsi32_si64(*(int*)(fref2 + (i + 1) * frefstride));
> + T12 = _mm_cvtsi32_si64(*(int*)(fref2 + (i + 2) * frefstride));
> + T13 = _mm_cvtsi32_si64(*(int*)(fref2 + (i + 3) * frefstride));
> + T14 = _mm_cvtsi32_si64(*(int*)(fref2 + (i + 4) * frefstride));
> + T15 = _mm_cvtsi32_si64(*(int*)(fref2 + (i + 5) * frefstride));
> + T16 = _mm_cvtsi32_si64(*(int*)(fref2 + (i + 6) * frefstride));
> + T17 = _mm_cvtsi32_si64(*(int*)(fref2 + (i + 7) * frefstride));
> +
> + T20 = _mm_sad_pu8(T00, T10);
> + T21 = _mm_sad_pu8(T01, T11);
> + T22 = _mm_sad_pu8(T02, T12);
> + T23 = _mm_sad_pu8(T03, T13);
> + T24 = _mm_sad_pu8(T04, T14);
> + T25 = _mm_sad_pu8(T05, T15);
> + T26 = _mm_sad_pu8(T06, T16);
> + T27 = _mm_sad_pu8(T07, T17);
> +
> + sum1 = _mm_add_pi16(sum1, T20);
> + sum1 = _mm_add_pi16(sum1, T21);
> + sum1 = _mm_add_pi16(sum1, T22);
> + sum1 = _mm_add_pi16(sum1, T23);
> + sum1 = _mm_add_pi16(sum1, T24);
> + sum1 = _mm_add_pi16(sum1, T25);
> + sum1 = _mm_add_pi16(sum1, T26);
> + sum1 = _mm_add_pi16(sum1, T27);
> +
> + T10 = _mm_cvtsi32_si64(*(int*)(fref2 + (i + 8) * frefstride));
> + T11 = _mm_cvtsi32_si64(*(int*)(fref2 + (i + 9) * frefstride));
> + T12 = _mm_cvtsi32_si64(*(int*)(fref2 + (i + 10) *
> frefstride));
> + T13 = _mm_cvtsi32_si64(*(int*)(fref2 + (i + 11) *
> frefstride));
> + T14 = _mm_cvtsi32_si64(*(int*)(fref2 + (i + 12) *
> frefstride));
> + T15 = _mm_cvtsi32_si64(*(int*)(fref2 + (i + 13) *
> frefstride));
> + T16 = _mm_cvtsi32_si64(*(int*)(fref2 + (i + 14) *
> frefstride));
> + T17 = _mm_cvtsi32_si64(*(int*)(fref2 + (i + 15) *
> frefstride));
> +
> + T20 = _mm_sad_pu8(T0, T10);
> + T21 = _mm_sad_pu8(T1, T11);
> + T22 = _mm_sad_pu8(T2, T12);
> + T23 = _mm_sad_pu8(T3, T13);
> + T24 = _mm_sad_pu8(T4, T14);
> + T25 = _mm_sad_pu8(T5, T15);
> + T26 = _mm_sad_pu8(T6, T16);
> + T27 = _mm_sad_pu8(T7, T17);
> +
> + sum1 = _mm_add_pi16(sum1, T20);
> + sum1 = _mm_add_pi16(sum1, T21);
> + sum1 = _mm_add_pi16(sum1, T22);
> + sum1 = _mm_add_pi16(sum1, T23);
> + sum1 = _mm_add_pi16(sum1, T24);
> + sum1 = _mm_add_pi16(sum1, T25);
> + sum1 = _mm_add_pi16(sum1, T26);
> + sum1 = _mm_add_pi16(sum1, T27);
> + res[1] = _m_to_int(sum1);
> +
> + T10 = _mm_cvtsi32_si64(*(int*)(fref3 + (i + 0) * frefstride));
> + T11 = _mm_cvtsi32_si64(*(int*)(fref3 + (i + 1) * frefstride));
> + T12 = _mm_cvtsi32_si64(*(int*)(fref3 + (i + 2) * frefstride));
> + T13 = _mm_cvtsi32_si64(*(int*)(fref3 + (i + 3) * frefstride));
> + T14 = _mm_cvtsi32_si64(*(int*)(fref3 + (i + 4) * frefstride));
> + T15 = _mm_cvtsi32_si64(*(int*)(fref3 + (i + 5) * frefstride));
> + T16 = _mm_cvtsi32_si64(*(int*)(fref3 + (i + 6) * frefstride));
> + T17 = _mm_cvtsi32_si64(*(int*)(fref3 + (i + 7) * frefstride));
> +
> + T20 = _mm_sad_pu8(T00, T10);
> + T21 = _mm_sad_pu8(T01, T11);
> + T22 = _mm_sad_pu8(T02, T12);
> + T23 = _mm_sad_pu8(T03, T13);
> + T24 = _mm_sad_pu8(T04, T14);
> + T25 = _mm_sad_pu8(T05, T15);
> + T26 = _mm_sad_pu8(T06, T16);
> + T27 = _mm_sad_pu8(T07, T17);
> +
> + sum2 = _mm_add_pi16(sum2, T20);
> + sum2 = _mm_add_pi16(sum2, T21);
> + sum2 = _mm_add_pi16(sum2, T22);
> + sum2 = _mm_add_pi16(sum2, T23);
> + sum2 = _mm_add_pi16(sum2, T24);
> + sum2 = _mm_add_pi16(sum2, T25);
> + sum2 = _mm_add_pi16(sum2, T26);
> + sum2 = _mm_add_pi16(sum2, T27);
> +
> + T10 = _mm_cvtsi32_si64(*(int*)(fref3 + (i + 8) * frefstride));
> + T11 = _mm_cvtsi32_si64(*(int*)(fref3 + (i + 9) * frefstride));
> + T12 = _mm_cvtsi32_si64(*(int*)(fref3 + (i + 10) *
> frefstride));
> + T13 = _mm_cvtsi32_si64(*(int*)(fref3 + (i + 11) *
> frefstride));
> + T14 = _mm_cvtsi32_si64(*(int*)(fref3 + (i + 12) *
> frefstride));
> + T15 = _mm_cvtsi32_si64(*(int*)(fref3 + (i + 13) *
> frefstride));
> + T16 = _mm_cvtsi32_si64(*(int*)(fref3 + (i + 14) *
> frefstride));
> + T17 = _mm_cvtsi32_si64(*(int*)(fref3 + (i + 15) *
> frefstride));
> +
> + T20 = _mm_sad_pu8(T0, T10);
> + T21 = _mm_sad_pu8(T1, T11);
> + T22 = _mm_sad_pu8(T2, T12);
> + T23 = _mm_sad_pu8(T3, T13);
> + T24 = _mm_sad_pu8(T4, T14);
> + T25 = _mm_sad_pu8(T5, T15);
> + T26 = _mm_sad_pu8(T6, T16);
> + T27 = _mm_sad_pu8(T7, T17);
> +
> + sum2 = _mm_add_pi16(sum2, T20);
> + sum2 = _mm_add_pi16(sum2, T21);
> + sum2 = _mm_add_pi16(sum2, T22);
> + sum2 = _mm_add_pi16(sum2, T23);
> + sum2 = _mm_add_pi16(sum2, T24);
> + sum2 = _mm_add_pi16(sum2, T25);
> + sum2 = _mm_add_pi16(sum2, T26);
> + sum2 = _mm_add_pi16(sum2, T27);
> + res[2] = _m_to_int(sum2);
> + }
> + }
> + else if ((ly % 8) == 0)
> + {
> + for (int i = 0; i < ly; i += 8)
> + {
> + T00 = _mm_cvtsi32_si64(*(int*)(fenc + (i + 0) * FENC_STRIDE));
> + T01 = _mm_cvtsi32_si64(*(int*)(fenc + (i + 1) * FENC_STRIDE));
> + T02 = _mm_cvtsi32_si64(*(int*)(fenc + (i + 2) * FENC_STRIDE));
> + T03 = _mm_cvtsi32_si64(*(int*)(fenc + (i + 3) * FENC_STRIDE));
> + T04 = _mm_cvtsi32_si64(*(int*)(fenc + (i + 4) * FENC_STRIDE));
> + T05 = _mm_cvtsi32_si64(*(int*)(fenc + (i + 5) * FENC_STRIDE));
> + T06 = _mm_cvtsi32_si64(*(int*)(fenc + (i + 6) * FENC_STRIDE));
> + T07 = _mm_cvtsi32_si64(*(int*)(fenc + (i + 7) * FENC_STRIDE));
> +
> + T10 = _mm_cvtsi32_si64(*(int*)(fref1 + (i + 0) * frefstride));
> + T11 = _mm_cvtsi32_si64(*(int*)(fref1 + (i + 1) * frefstride));
> + T12 = _mm_cvtsi32_si64(*(int*)(fref1 + (i + 2) * frefstride));
> + T13 = _mm_cvtsi32_si64(*(int*)(fref1 + (i + 3) * frefstride));
> + T14 = _mm_cvtsi32_si64(*(int*)(fref1 + (i + 4) * frefstride));
> + T15 = _mm_cvtsi32_si64(*(int*)(fref1 + (i + 5) * frefstride));
> + T16 = _mm_cvtsi32_si64(*(int*)(fref1 + (i + 6) * frefstride));
> + T17 = _mm_cvtsi32_si64(*(int*)(fref1 + (i + 7) * frefstride));
> +
> + T20 = _mm_sad_pu8(T00, T10);
> + T21 = _mm_sad_pu8(T01, T11);
> + T22 = _mm_sad_pu8(T02, T12);
> + T23 = _mm_sad_pu8(T03, T13);
> + T24 = _mm_sad_pu8(T04, T14);
> + T25 = _mm_sad_pu8(T05, T15);
> + T26 = _mm_sad_pu8(T06, T16);
> + T27 = _mm_sad_pu8(T07, T17);
> +
> + sum0 = _mm_add_pi16(sum0, T20);
> + sum0 = _mm_add_pi16(sum0, T21);
> + sum0 = _mm_add_pi16(sum0, T22);
> + sum0 = _mm_add_pi16(sum0, T23);
> + sum0 = _mm_add_pi16(sum0, T24);
> + sum0 = _mm_add_pi16(sum0, T25);
> + sum0 = _mm_add_pi16(sum0, T26);
> + sum0 = _mm_add_pi16(sum0, T27);
> + res[0] = _m_to_int(sum0);
> +
> + T10 = _mm_cvtsi32_si64(*(int*)(fref2 + (i + 0) * frefstride));
> + T11 = _mm_cvtsi32_si64(*(int*)(fref2 + (i + 1) * frefstride));
> + T12 = _mm_cvtsi32_si64(*(int*)(fref2 + (i + 2) * frefstride));
> + T13 = _mm_cvtsi32_si64(*(int*)(fref2 + (i + 3) * frefstride));
> + T14 = _mm_cvtsi32_si64(*(int*)(fref2 + (i + 4) * frefstride));
> + T15 = _mm_cvtsi32_si64(*(int*)(fref2 + (i + 5) * frefstride));
> + T16 = _mm_cvtsi32_si64(*(int*)(fref2 + (i + 6) * frefstride));
> + T17 = _mm_cvtsi32_si64(*(int*)(fref2 + (i + 7) * frefstride));
> +
> + T20 = _mm_sad_pu8(T00, T10);
> + T21 = _mm_sad_pu8(T01, T11);
> + T22 = _mm_sad_pu8(T02, T12);
> + T23 = _mm_sad_pu8(T03, T13);
> + T24 = _mm_sad_pu8(T04, T14);
> + T25 = _mm_sad_pu8(T05, T15);
> + T26 = _mm_sad_pu8(T06, T16);
> + T27 = _mm_sad_pu8(T07, T17);
> +
> + sum1 = _mm_add_pi16(sum1, T20);
> + sum1 = _mm_add_pi16(sum1, T21);
> + sum1 = _mm_add_pi16(sum1, T22);
> + sum1 = _mm_add_pi16(sum1, T23);
> + sum1 = _mm_add_pi16(sum1, T24);
> + sum1 = _mm_add_pi16(sum1, T25);
> + sum1 = _mm_add_pi16(sum1, T26);
> + sum1 = _mm_add_pi16(sum1, T27);
> + res[1] = _m_to_int(sum1);
> +
> + T10 = _mm_cvtsi32_si64(*(int*)(fref3 + (i + 0) * frefstride));
> + T11 = _mm_cvtsi32_si64(*(int*)(fref3 + (i + 1) * frefstride));
> + T12 = _mm_cvtsi32_si64(*(int*)(fref3 + (i + 2) * frefstride));
> + T13 = _mm_cvtsi32_si64(*(int*)(fref3 + (i + 3) * frefstride));
> + T14 = _mm_cvtsi32_si64(*(int*)(fref3 + (i + 4) * frefstride));
> + T15 = _mm_cvtsi32_si64(*(int*)(fref3 + (i + 5) * frefstride));
> + T16 = _mm_cvtsi32_si64(*(int*)(fref3 + (i + 6) * frefstride));
> + T17 = _mm_cvtsi32_si64(*(int*)(fref3 + (i + 7) * frefstride));
> +
> + T20 = _mm_sad_pu8(T00, T10);
> + T21 = _mm_sad_pu8(T01, T11);
> + T22 = _mm_sad_pu8(T02, T12);
> + T23 = _mm_sad_pu8(T03, T13);
> + T24 = _mm_sad_pu8(T04, T14);
> + T25 = _mm_sad_pu8(T05, T15);
> + T26 = _mm_sad_pu8(T06, T16);
> + T27 = _mm_sad_pu8(T07, T17);
> +
> + sum2 = _mm_add_pi16(sum2, T20);
> + sum2 = _mm_add_pi16(sum2, T21);
> + sum2 = _mm_add_pi16(sum2, T22);
> + sum2 = _mm_add_pi16(sum2, T23);
> + sum2 = _mm_add_pi16(sum2, T24);
> + sum2 = _mm_add_pi16(sum2, T25);
> + sum2 = _mm_add_pi16(sum2, T26);
> + sum2 = _mm_add_pi16(sum2, T27);
> + res[2] = _m_to_int(sum2);
> + }
> + }
> + else
> + {
> + for (int i = 0; i < ly; i += 4)
> + {
> + T00 = _mm_cvtsi32_si64(*(int*)(fenc + (i + 0) * FENC_STRIDE));
> + T01 = _mm_cvtsi32_si64(*(int*)(fenc + (i + 1) * FENC_STRIDE));
> + T02 = _mm_cvtsi32_si64(*(int*)(fenc + (i + 2) * FENC_STRIDE));
> + T03 = _mm_cvtsi32_si64(*(int*)(fenc + (i + 3) * FENC_STRIDE));
> +
> + T10 = _mm_cvtsi32_si64(*(int*)(fref1 + (i + 0) * frefstride));
> + T11 = _mm_cvtsi32_si64(*(int*)(fref1 + (i + 1) * frefstride));
> + T12 = _mm_cvtsi32_si64(*(int*)(fref1 + (i + 2) * frefstride));
> + T13 = _mm_cvtsi32_si64(*(int*)(fref1 + (i + 3) * frefstride));
> +
> + T20 = _mm_sad_pu8(T00, T10);
> + T21 = _mm_sad_pu8(T01, T11);
> + T22 = _mm_sad_pu8(T02, T12);
> + T23 = _mm_sad_pu8(T03, T13);
> +
> + sum0 = _mm_add_pi16(sum0, T20);
> + sum0 = _mm_add_pi16(sum0, T21);
> + sum0 = _mm_add_pi16(sum0, T22);
> + sum0 = _mm_add_pi16(sum0, T23);
> + res[0] = _m_to_int(sum0);
> +
> + T10 = _mm_cvtsi32_si64(*(int*)(fref2 + (i + 0) * frefstride));
> + T11 = _mm_cvtsi32_si64(*(int*)(fref2 + (i + 1) * frefstride));
> + T12 = _mm_cvtsi32_si64(*(int*)(fref2 + (i + 2) * frefstride));
> + T13 = _mm_cvtsi32_si64(*(int*)(fref2 + (i + 3) * frefstride));
> +
> + T20 = _mm_sad_pu8(T00, T10);
> + T21 = _mm_sad_pu8(T01, T11);
> + T22 = _mm_sad_pu8(T02, T12);
> + T23 = _mm_sad_pu8(T03, T13);
> +
> + sum1 = _mm_add_pi16(sum1, T20);
> + sum1 = _mm_add_pi16(sum1, T21);
> + sum1 = _mm_add_pi16(sum1, T22);
> + sum1 = _mm_add_pi16(sum1, T23);
> + res[1] = _m_to_int(sum1);
> +
> + T10 = _mm_cvtsi32_si64(*(int*)(fref3 + (i + 0) * frefstride));
> + T11 = _mm_cvtsi32_si64(*(int*)(fref3 + (i + 1) * frefstride));
> + T12 = _mm_cvtsi32_si64(*(int*)(fref3 + (i + 2) * frefstride));
> + T13 = _mm_cvtsi32_si64(*(int*)(fref3 + (i + 3) * frefstride));
> +
> + T20 = _mm_sad_pu8(T00, T10);
> + T21 = _mm_sad_pu8(T01, T11);
> + T22 = _mm_sad_pu8(T02, T12);
> + T23 = _mm_sad_pu8(T03, T13);
> +
> + sum2 = _mm_add_pi16(sum2, T20);
> + sum2 = _mm_add_pi16(sum2, T21);
> + sum2 = _mm_add_pi16(sum2, T22);
> + sum2 = _mm_add_pi16(sum2, T23);
> + res[2] = _m_to_int(sum2);
> + }
> + }
> +}
> +
> +#endif /* ifdef X86_64 */
> +
> template<int ly>
> void sad_x3_8(pixel *fenc, pixel *fref1, pixel *fref2, pixel *fref3,
> intptr_t frefstride, int *res)
> {
> _______________________________________________
> x265-devel mailing list
> x265-devel at videolan.org
> https://mailman.videolan.org/listinfo/x265-devel
>
--
Steve Borho
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