[x265] [PATCH] asm: 10bpp code of sse_ss for 12x16, 24x32, 48x64 and 64xN blocks

[chen]

>+%macro SSD_TWO 2
>+cglobal pixel_ssd_ss_%1x%2, 4,7,6
>+    FIX_STRIDES r1, r3
>+    pxor    m0,  m0
>+    mov     r4d, %2/2
>+    lea     r5,  [r1 * 2]
>+    lea     r6,  [r3 * 2]
>+.loop
>+    mova    m1,  [r0]
>+    mova    m2,  [r0 + 16]
>+    mova    m3,  [r0 + 32]
>+    mova    m4,  [r0 + 48]
>+    psubw   m1,  [r2]
>+    psubw   m2,  [r2 + 16]
>+    psubw   m3,  [r2 + 32]
>+    psubw   m4,  [r2 + 48]
This style need memory is alignment, please check and confirm it in our encoder.
 
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