[x265] [PATCH] asm: 10bpp code for pixel_add_ps_6x8
murugan at multicorewareinc.com
murugan at multicorewareinc.com
Mon Dec 9 11:21:03 CET 2013
# HG changeset patch
# User Murugan Vairavel <murugan at multicorewareinc.com>
# Date 1386584397 -19800
# Mon Dec 09 15:49:57 2013 +0530
# Node ID 83491f85c0c8449161b0c26850cfe92c9de9728e
# Parent 5bb46ef28bc59794404e59de5c62188928685437
asm: 10bpp code for pixel_add_ps_6x8
diff -r 5bb46ef28bc5 -r 83491f85c0c8 source/common/x86/pixeladd8.asm
--- a/source/common/x86/pixeladd8.asm Mon Dec 09 10:59:45 2013 +0800
+++ b/source/common/x86/pixeladd8.asm Mon Dec 09 15:49:57 2013 +0530
@@ -364,6 +364,51 @@
; void pixel_add_ps_%1x%2(pixel *dest, intptr_t destride, pixel *src0, int16_t *scr1, intptr_t srcStride0, intptr_t srcStride1)
;-----------------------------------------------------------------------------
%macro PIXEL_ADD_PS_W6_H4 2
+%if HIGH_BIT_DEPTH
+INIT_XMM sse2
+cglobal pixel_add_ps_%1x%2, 6, 7, 6, dest, destride, src0, scr1, srcStride0, srcStride1
+ mov r6d, %2/4
+ add r1, r1
+ add r4, r4
+ add r5, r5
+ pxor m4, m4
+ mova m5, [pw_pixel_max]
+.loop
+ movu m0, [r2]
+ movu m1, [r3]
+ movu m2, [r2 + r4]
+ movu m3, [r3 + r5]
+ paddw m0, m1
+ paddw m2, m3
+ CLIPW m0, m4, m5
+ CLIPW m2, m4, m5
+
+ movh [r0], m0
+ pshufd m1, m0, 2
+ movd [r0 + 8], m1
+ movh [r0 + r1], m2
+ pshufd m3, m2, 2
+ movd [r0 + r1 + 8], m3
+
+ lea r2, [r2 + 2 * r4]
+ lea r3, [r3 + 2 * r5]
+ lea r0, [r0 + 2 * r1]
+ movu m0, [r2]
+ movu m1, [r3]
+ movu m2, [r2 + r4]
+ movu m3, [r3 + r5]
+ paddw m0, m1
+ paddw m2, m3
+ CLIPW m0, m4, m5
+ CLIPW m2, m4, m5
+
+ movh [r0], m0
+ pshufd m1, m0, 2
+ movd [r0 + 8], m1
+ movh [r0 + r1], m2
+ pshufd m3, m2, 2
+ movd [r0 + r1 + 8], m3
+%else
INIT_XMM sse4
cglobal pixel_add_ps_%1x%2, 6, 7, 2, dest, destride, src0, scr1, srcStride0, srcStride1
@@ -411,7 +456,7 @@
movd [r0 + r1], m0
pextrw [r0 + r1 + 4], m0, 2
-
+%endif
lea r0, [r0 + 2 * r1]
lea r2, [r2 + 2 * r4]
lea r3, [r3 + 2 * r5]
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