[x265] [PATCH] asm code for blockcopy_sp, 24x32 block
praveen at multicorewareinc.com
praveen at multicorewareinc.com
Wed Nov 6 12:32:29 CET 2013
# HG changeset patch
# User Praveen Tiwari
# Date 1383737539 -19800
# Node ID abbce0280b6814cf3ef4064503194fd0ff5aa06e
# Parent 7486c5c64cc0666deab456aea12a2e1710873680
asm code for blockcopy_sp, 24x32 block
diff -r 7486c5c64cc0 -r abbce0280b68 source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Wed Nov 06 16:01:41 2013 +0530
+++ b/source/common/x86/asm-primitives.cpp Wed Nov 06 17:02:19 2013 +0530
@@ -344,6 +344,7 @@
p.chroma_copy_sp[CHROMA_16x12] = x265_blockcopy_sp_16x12_sse2;
p.chroma_copy_sp[CHROMA_16x16] = x265_blockcopy_sp_16x16_sse2;
p.chroma_copy_sp[CHROMA_16x32] = x265_blockcopy_sp_16x32_sse2;
+ p.chroma_copy_sp[CHROMA_24x32] = x265_blockcopy_sp_24x32_sse2;
#if X86_64
p.satd[LUMA_8x32] = x265_pixel_satd_8x32_sse2;
p.satd[LUMA_16x4] = x265_pixel_satd_16x4_sse2;
diff -r 7486c5c64cc0 -r abbce0280b68 source/common/x86/blockcopy8.asm
--- a/source/common/x86/blockcopy8.asm Wed Nov 06 16:01:41 2013 +0530
+++ b/source/common/x86/blockcopy8.asm Wed Nov 06 17:02:19 2013 +0530
@@ -1207,3 +1207,49 @@
BLOCKCOPY_SP_W16_H4 16, 12
BLOCKCOPY_SP_W16_H4 16, 16
BLOCKCOPY_SP_W16_H4 16, 32
+
+;-----------------------------------------------------------------------------
+; void blockcopy_sp_%1x%2(pixel *dest, intptr_t destStride, int16_t *src, intptr_t srcStride)
+;-----------------------------------------------------------------------------
+%macro BLOCKCOPY_SP_W24_H2 2
+INIT_XMM sse2
+cglobal blockcopy_sp_%1x%2, 4, 5, 7, dest, destStride, src, srcStride
+
+mov r4d, %2
+
+add r3, r3
+
+mova m0, [tab_Vm]
+
+.loop
+ movu m1, [r2]
+ movu m2, [r2 + 16]
+ movu m3, [r2 + 32]
+ movu m4, [r2 + r3]
+ movu m5, [r2 + r3 + 16]
+ movu m6, [r2 + r3 + 32]
+
+ pshufb m1, m0
+ pshufb m2, m0
+ pshufb m3, m0
+ pshufb m4, m0
+ pshufb m5, m0
+ pshufb m6, m0
+
+ movh [r0], m1
+ movh [r0 + 8], m2
+ movh [r0 + 16], m3
+ movh [r0 + r1], m4
+ movh [r0 + r1 + 8], m5
+ movh [r0 + r1 + 16], m6
+
+ lea r0, [r0 + 2 * r1]
+ lea r2, [r2 + 2 * r3]
+
+ sub r4d, 2
+ jnz .loop
+
+RET
+%endmacro
+
+BLOCKCOPY_SP_W24_H2 24, 32
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