[x265] [PATCH Review only] asm: pixelsub_ps routine for 4xN blocks
murugan at multicorewareinc.com
murugan at multicorewareinc.com
Fri Nov 8 11:03:27 CET 2013
# HG changeset patch
# User Murugan Vairavel <murugan at multicorewareinc.com>
# Date 1383904977 -19800
# Fri Nov 08 15:32:57 2013 +0530
# Node ID 673977c209a0d54423def33a0aabbd3b86c41e5f
# Parent f9f2f6f78b50cf0eb0fd40b1f0b3508e810e1197
asm: pixelsub_ps routine for 4xN blocks
diff -r f9f2f6f78b50 -r 673977c209a0 source/common/x86/pixel-a.asm
--- a/source/common/x86/pixel-a.asm Fri Nov 08 14:18:08 2013 +0530
+++ b/source/common/x86/pixel-a.asm Fri Nov 08 15:32:57 2013 +0530
@@ -5284,3 +5284,137 @@
jl .loop
movifnidn eax, r0d
RET
+
+;-----------------------------------------------------------------------------
+; void pixel_sub_sp_c_4x2(int16_t *dest, intptr_t destride, pixel *src0, pixel *src1, intptr_t srcstride0, intptr_t srcstride1);
+;-----------------------------------------------------------------------------
+INIT_XMM sse4
+cglobal pixel_sub_ps_4x2, 6, 6, 4, dest, deststride, src0, src1, srcstride0, srcstride1
+
+add r1, r1
+
+movd m0, [r2]
+movd m1, [r3]
+
+movd m2, [r2 + r4]
+movd m3, [r3 + r5]
+
+punpckldq m0, m2
+punpckldq m1, m3
+pmovzxbw m0, m0
+pmovzxbw m1, m1
+
+psubw m0, m1
+
+movlps [r0], m0
+movhps [r0 + r1], m0
+
+RET
+
+;-----------------------------------------------------------------------------
+; void pixel_sub_ps_c_4x4(int16_t *dest, intptr_t destride, pixel *src0, pixel *src1, intptr_t srcstride0, intptr_t srcstride1);
+;-----------------------------------------------------------------------------
+INIT_XMM sse4
+cglobal pixel_sub_ps_4x4, 6, 6, 8, dest, deststride, src0, src1, srcstride0, srcstride1
+
+add r1, r1
+
+movd m0, [r2]
+movd m1, [r3]
+
+movd m2, [r2 + r4]
+movd m3, [r3 + r5]
+
+movd m4, [r2 + 2 * r4]
+movd m5, [r3 + 2 * r5]
+
+lea r2, [r2 + 2 * r4]
+lea r3, [r3 + 2 * r5]
+
+movd m6, [r2 + r4]
+movd m7, [r3 + r5]
+
+punpckldq m0, m2
+punpckldq m1, m3
+punpckldq m4, m6
+punpckldq m5, m7
+
+pmovzxbw m0, m0
+pmovzxbw m1, m1
+pmovzxbw m4, m4
+pmovzxbw m5, m5
+
+psubw m0, m1
+psubw m4, m5
+
+movlps [r0], m0
+movhps [r0 + r1], m0
+movlps [r0 + 2 * r1], m4
+
+lea r0, [r0 + 2 * r1]
+
+movhps [r0 + r1], m4
+
+RET
+
+;-----------------------------------------------------------------------------
+; void pixel_sub_ps_c_%1x%2(pixel *dest, intptr_t destride, pixel *src0, pixel *src1, intptr_t srcstride0, intptr_t srcstride1);
+;-----------------------------------------------------------------------------
+%macro PIXELSUB_PS_W4_H4 2
+INIT_XMM sse4
+cglobal pixel_sub_ps_%1x%2, 6, 7, 8, dest, deststride, src0, src1, srcstride0, srcstride1
+
+add r1, r1
+mov r6d, %2
+
+.loop
+
+ movd m0, [r2]
+ movd m1, [r3]
+
+ movd m2, [r2 + r4]
+ movd m3, [r3 + r5]
+
+ movd m4, [r2 + 2 * r4]
+ movd m5, [r3 + 2 * r5]
+
+ lea r2, [r2 + 2 * r4]
+ lea r3, [r3 + 2 * r5]
+
+ movd m6, [r2 + r4]
+ movd m7, [r3 + r5]
+
+ punpckldq m0, m2
+ punpckldq m1, m3
+ punpckldq m4, m6
+ punpckldq m5, m7
+
+ pmovzxbw m0, m0
+ pmovzxbw m1, m1
+ pmovzxbw m4, m4
+ pmovzxbw m5, m5
+
+ psubw m0, m1
+ psubw m4, m5
+
+ movlps [r0], m0
+ movhps [r0 + r1], m0
+ movlps [r0 + 2 * r1], m4
+
+ lea r0, [r0 + 2 * r1]
+
+ movhps [r0 + r1], m4
+
+ lea r2, [r2 + 2 * r4]
+ lea r3, [r3 + 2 * r5]
+ lea r0, [r0 + 2 * r1]
+
+ sub r6d, 4
+
+jnz .loop
+
+RET
+%endmacro
+
+PIXELSUB_PS_W4_H4 4, 8
+PIXELSUB_PS_W4_H4 4, 16
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