[x265] [PATCH Review only] asm: pixelsub_ps routine for 2xN blocks

[murugan at multicorewareinc.com]

# HG changeset patch
# User Murugan Vairavel <murugan at multicorewareinc.com>
# Date 1384175456 -19800
#      Mon Nov 11 18:40:56 2013 +0530
# Node ID fa2a0c6166d816d6d5a698e1386bbf412ed5f722
# Parent  2dfda7d0c819c026f8ad41bced831672a02976f2
asm: pixelsub_ps routine for 2xN blocks

diff -r 2dfda7d0c819 -r fa2a0c6166d8 source/common/x86/pixel-a.asm
--- a/source/common/x86/pixel-a.asm	Mon Nov 11 16:39:42 2013 +0530
+++ b/source/common/x86/pixel-a.asm	Mon Nov 11 18:40:56 2013 +0530
@@ -5286,6 +5286,113 @@
     RET
 
 ;-----------------------------------------------------------------------------
+; void pixel_sub_ps_c_2x4(int16_t *dest, intptr_t destride, pixel *src0, pixel *src1, intptr_t srcstride0, intptr_t srcstride1);
+;-----------------------------------------------------------------------------
+INIT_XMM sse4
+cglobal pixel_sub_ps_2x4, 6, 7, 2, dest, deststride, src0, src1, srcstride0, srcstride1
+
+add         r1,    r1
+
+movd        m0,    [r2]
+movd        m1,    [r2 + r4]
+movd        m2,    [r2 + 2 * r4]
+
+movd        m3,    [r3]
+movd        m4,    [r3 + r5]
+movd        m5,    [r3 + 2 * r5]
+
+lea         r2,    [r2 + 2 * r4]
+lea         r3,    [r3 + 2 * r5]
+
+movd        m6,    [r2 + r4]
+movd        m7,    [r3 + r5]
+
+pmovzxbw    m0,    m0
+pmovzxbw    m1,    m1
+pmovzxbw    m2,    m2
+pmovzxbw    m3,    m3
+pmovzxbw    m4,    m4
+pmovzxbw    m5,    m5
+pmovzxbw    m6,    m6
+pmovzxbw    m7,    m7
+
+psubw       m0,    m3
+psubw       m1,    m4
+psubw       m2,    m5
+psubw       m6,    m7
+
+movd    [r0],            m0
+movd    [r0 + r1],       m1
+movd    [r0 + 2* r1],    m2
+
+lea     r0,              [r0 + 2 * r1]
+
+movd    [r0 + r1],       m6
+
+RET
+
+;-----------------------------------------------------------------------------
+; void pixel_sub_ps_c_%1x%2(pixel *dest, intptr_t destride, pixel *src0, pixel *src1, intptr_t srcstride0, intptr_t srcstride1);
+;-----------------------------------------------------------------------------
+%macro PIXELSUB_PS_W2_H4 2
+INIT_XMM sse4
+cglobal pixel_sub_ps_%1x%2, 6, 7, 8, dest, deststride, src0, src1, srcstride0, srcstride1
+
+add    r1,     r1
+mov    r6d,    %2/4
+
+.loop
+
+    movd        m0,    [r2]
+    movd        m1,    [r2 + r4]
+    movd        m2,    [r2 + 2 * r4]
+
+    movd        m3,    [r3]
+    movd        m4,    [r3 + r5]
+    movd        m5,    [r3 + 2 * r5]
+
+    lea         r2,    [r2 + 2 * r4]
+    lea         r3,    [r3 + 2 * r5]
+
+    movd        m6,    [r2 + r4]
+    movd        m7,    [r3 + r5]
+
+    pmovzxbw    m0,    m0
+    pmovzxbw    m1,    m1
+    pmovzxbw    m2,    m2
+    pmovzxbw    m3,    m3
+    pmovzxbw    m4,    m4
+    pmovzxbw    m5,    m5
+    pmovzxbw    m6,    m6
+    pmovzxbw    m7,    m7
+
+    psubw       m0,    m3
+    psubw       m1,    m4
+    psubw       m2,    m5
+    psubw       m6,    m7
+
+    movd    [r0],            m0
+    movd    [r0 + r1],       m1
+    movd    [r0 + 2* r1],    m2
+
+    lea     r0,              [r0 + 2 * r1]
+
+    movd    [r0 + r1],       m6
+
+    lea     r2,              [r2 + 2 * r4]
+    lea     r3,              [r3 + 2 * r5]
+    lea     r0,              [r0 + 2 * r1]
+
+    dec     r6d
+
+jnz    .loop
+
+RET
+%endmacro
+
+PIXELSUB_PS_W2_H4 2, 8
+
+;-----------------------------------------------------------------------------
 ; void pixel_sub_sp_c_4x2(int16_t *dest, intptr_t destride, pixel *src0, pixel *src1, intptr_t srcstride0, intptr_t srcstride1);
 ;-----------------------------------------------------------------------------
 INIT_XMM sse4