[x265] [PATCH Review only] asm: code for sse_pp_48x64 routine

murugan at multicorewareinc.com murugan at multicorewareinc.com
Fri Nov 22 11:47:12 CET 2013


# HG changeset patch
# User Murugan Vairavel <murugan at multicorewareinc.com>
# Date 1385117208 -19800
#      Fri Nov 22 16:16:48 2013 +0530
# Node ID 45ad44be1b151ec43ac36069ae1c8cf4913855ad
# Parent  617189df07a7d24642622a5e474007ad34bbc9f4
asm: code for sse_pp_48x64 routine

diff -r 617189df07a7 -r 45ad44be1b15 source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp	Fri Nov 22 15:31:41 2013 +0530
+++ b/source/common/x86/asm-primitives.cpp	Fri Nov 22 16:16:48 2013 +0530
@@ -605,6 +605,7 @@
 
         p.sse_pp[LUMA_12x16] = x265_pixel_ssd_12x16_sse4;
         p.sse_pp[LUMA_24x32] = x265_pixel_ssd_24x32_sse4;
+        p.sse_pp[LUMA_48x64] = x265_pixel_ssd_48x64_sse4;
 
         CHROMA_PIXELSUB_PS(_sse4);
 
diff -r 617189df07a7 -r 45ad44be1b15 source/common/x86/pixel-a.asm
--- a/source/common/x86/pixel-a.asm	Fri Nov 22 15:31:41 2013 +0530
+++ b/source/common/x86/pixel-a.asm	Fri Nov 22 16:16:48 2013 +0530
@@ -678,6 +678,138 @@
 
     RET
 
+%macro PIXEL_SSD_16x4 0
+
+    movu         m1,    [r0]
+    pmovzxbw     m0,    m1
+    punpckhbw    m1,    m6
+    movu         m3,    [r2]
+    pmovzxbw     m2,    m3
+    punpckhbw    m3,    m6
+
+    psubw        m0,    m2
+    psubw        m1,    m3
+
+    movu         m5,    [r0 + r1]
+    pmovzxbw     m4,    m5
+    punpckhbw    m5,    m6
+    movu         m3,    [r2 + r3]
+    pmovzxbw     m2,    m3
+    punpckhbw    m3,    m6
+
+    psubw        m4,    m2
+    psubw        m5,    m3
+
+    pmaddwd      m0,    m0
+    pmaddwd      m1,    m1
+    pmaddwd      m4,    m4
+    pmaddwd      m5,    m5
+
+    paddd        m0,    m1
+    paddd        m4,    m5
+    paddd        m4,    m0
+    paddd        m7,    m4
+
+    movu         m1,    [r0 + r6]
+    pmovzxbw     m0,    m1
+    punpckhbw    m1,    m6
+    movu         m3,    [r2 + 2 * r3]
+    pmovzxbw     m2,    m3
+    punpckhbw    m3,    m6
+
+    psubw        m0,    m2
+    psubw        m1,    m3
+
+    lea          r0,    [r0 + r6]
+    lea          r2,    [r2 + 2 * r3]
+
+    movu         m5,    [r0 + r1]
+    pmovzxbw     m4,    m5
+    punpckhbw    m5,    m6
+    movu         m3,    [r2 + r3]
+    pmovzxbw     m2,    m3
+    punpckhbw    m3,    m6
+
+    psubw        m4,    m2
+    psubw        m5,    m3
+
+    pmaddwd      m0,    m0
+    pmaddwd      m1,    m1
+    pmaddwd      m4,    m4
+    pmaddwd      m5,    m5
+
+    paddd        m0,    m1
+    paddd        m4,    m5
+    paddd        m4,    m0
+    paddd        m7,    m4
+
+%endmacro
+
+cglobal pixel_ssd_16x16_internal
+    PIXEL_SSD_16x4
+    lea     r0,    [r0 + r6]
+    lea     r2,    [r2 + 2 * r3]
+    PIXEL_SSD_16x4
+    lea     r0,    [r0 + r6]
+    lea     r2,    [r2 + 2 * r3]
+    PIXEL_SSD_16x4
+    lea     r0,    [r0 + r6]
+    lea     r2,    [r2 + 2 * r3]
+    PIXEL_SSD_16x4
+    ret
+
+;-----------------------------------------------------------------------------
+; int pixel_ssd_48x64( uint8_t *, intptr_t, uint8_t *, intptr_t )
+;-----------------------------------------------------------------------------
+INIT_XMM sse4
+cglobal pixel_ssd_48x64, 4, 7, 8, src1, stride1, src2, stride2
+
+    pxor    m7,    m7
+    pxor    m6,    m6
+    mov     r4,    r0
+    mov     r5,    r2
+    mov     r6,    r1
+    add     r6,    r6
+    call    pixel_ssd_16x16_internal
+    lea     r0,    [r0 + r6]
+    lea     r2,    [r2 + 2 * r3]
+    call    pixel_ssd_16x16_internal
+    lea     r0,    [r0 + r6]
+    lea     r2,    [r2 + 2 * r3]
+    call    pixel_ssd_16x16_internal
+    lea     r0,    [r0 + r6]
+    lea     r2,    [r2 + 2 * r3]
+    call    pixel_ssd_16x16_internal
+    lea     r0,    [r4 + 16]
+    lea     r2,    [r5 + 16]
+    call    pixel_ssd_16x16_internal
+    lea     r0,    [r0 + r6]
+    lea     r2,    [r2 + 2 * r3]
+    call    pixel_ssd_16x16_internal
+    lea     r0,    [r0 + r6]
+    lea     r2,    [r2 + 2 * r3]
+    call    pixel_ssd_16x16_internal
+    lea     r0,    [r0 + r6]
+    lea     r2,    [r2 + 2 * r3]
+    call    pixel_ssd_16x16_internal
+    lea     r0,    [r4 + 32]
+    lea     r2,    [r5 + 32]
+    call    pixel_ssd_16x16_internal
+    lea     r0,    [r0 + r6]
+    lea     r2,    [r2 + 2 * r3]
+    call    pixel_ssd_16x16_internal
+    lea     r0,    [r0 + r6]
+    lea     r2,    [r2 + 2 * r3]
+    call    pixel_ssd_16x16_internal
+    lea     r0,    [r0 + r6]
+    lea     r2,    [r2 + 2 * r3]
+    call    pixel_ssd_16x16_internal
+
+    HADDD   m7, m1
+    movd   eax, m7
+
+    RET
+
 ;-----------------------------------------------------------------------------
 ; void pixel_ssd_nv12_core( uint16_t *pixuv1, intptr_t stride1, uint16_t *pixuv2, intptr_t stride2,
 ;                           int width, int height, uint64_t *ssd_u, uint64_t *ssd_v )
diff -r 617189df07a7 -r 45ad44be1b15 source/common/x86/pixel.h
--- a/source/common/x86/pixel.h	Fri Nov 22 15:31:41 2013 +0530
+++ b/source/common/x86/pixel.h	Fri Nov 22 16:16:48 2013 +0530
@@ -374,5 +374,6 @@
 void x265_transpose64_sse2(pixel *dest, pixel *src, intptr_t stride);
 int x265_pixel_ssd_12x16_sse4(pixel *, intptr_t, pixel *, intptr_t);
 int x265_pixel_ssd_24x32_sse4(pixel *, intptr_t, pixel *, intptr_t);
+int x265_pixel_ssd_48x64_sse4(pixel *, intptr_t, pixel *, intptr_t);
 
 #endif // ifndef X265_I386_PIXEL_H


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