[x265] [PATCH] asm: code of sse_pp routine for 48x64 and 64x16 blocks
murugan at multicorewareinc.com
murugan at multicorewareinc.com
Fri Nov 22 13:10:11 CET 2013
# HG changeset patch
# User Murugan Vairavel <murugan at multicorewareinc.com>
# Date 1385122195 -19800
# Fri Nov 22 17:39:55 2013 +0530
# Node ID 37238c6124be44fdbeca53411dd35be3b938b38d
# Parent 81ecfb791aec1c9294816929f6e25c7e0e3d9884
asm: code of sse_pp routine for 48x64 and 64x16 blocks
diff -r 81ecfb791aec -r 37238c6124be source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Fri Nov 22 17:14:32 2013 +0530
+++ b/source/common/x86/asm-primitives.cpp Fri Nov 22 17:39:55 2013 +0530
@@ -605,6 +605,8 @@
p.sse_pp[LUMA_12x16] = x265_pixel_ssd_12x16_sse4;
p.sse_pp[LUMA_24x32] = x265_pixel_ssd_24x32_sse4;
+ p.sse_pp[LUMA_48x64] = x265_pixel_ssd_48x64_sse4;
+ p.sse_pp[LUMA_64x16] = x265_pixel_ssd_64x16_sse4;
CHROMA_PIXELSUB_PS(_sse4);
diff -r 81ecfb791aec -r 37238c6124be source/common/x86/pixel-a.asm
--- a/source/common/x86/pixel-a.asm Fri Nov 22 17:14:32 2013 +0530
+++ b/source/common/x86/pixel-a.asm Fri Nov 22 17:39:55 2013 +0530
@@ -674,6 +674,163 @@
RET
+%macro PIXEL_SSD_16x4 0
+ movu m1, [r0]
+ pmovzxbw m0, m1
+ punpckhbw m1, m6
+ movu m3, [r2]
+ pmovzxbw m2, m3
+ punpckhbw m3, m6
+
+ psubw m0, m2
+ psubw m1, m3
+
+ movu m5, [r0 + r1]
+ pmovzxbw m4, m5
+ punpckhbw m5, m6
+ movu m3, [r2 + r3]
+ pmovzxbw m2, m3
+ punpckhbw m3, m6
+
+ psubw m4, m2
+ psubw m5, m3
+
+ pmaddwd m0, m0
+ pmaddwd m1, m1
+ pmaddwd m4, m4
+ pmaddwd m5, m5
+
+ paddd m0, m1
+ paddd m4, m5
+ paddd m4, m0
+ paddd m7, m4
+
+ movu m1, [r0 + r6]
+ pmovzxbw m0, m1
+ punpckhbw m1, m6
+ movu m3, [r2 + 2 * r3]
+ pmovzxbw m2, m3
+ punpckhbw m3, m6
+
+ psubw m0, m2
+ psubw m1, m3
+
+ lea r0, [r0 + r6]
+ lea r2, [r2 + 2 * r3]
+ movu m5, [r0 + r1]
+ pmovzxbw m4, m5
+ punpckhbw m5, m6
+ movu m3, [r2 + r3]
+ pmovzxbw m2, m3
+ punpckhbw m3, m6
+
+ psubw m4, m2
+ psubw m5, m3
+
+ pmaddwd m0, m0
+ pmaddwd m1, m1
+ pmaddwd m4, m4
+ pmaddwd m5, m5
+
+ paddd m0, m1
+ paddd m4, m5
+ paddd m4, m0
+ paddd m7, m4
+%endmacro
+
+cglobal pixel_ssd_16x16_internal
+ PIXEL_SSD_16x4
+ lea r0, [r0 + r6]
+ lea r2, [r2 + 2 * r3]
+ PIXEL_SSD_16x4
+ lea r0, [r0 + r6]
+ lea r2, [r2 + 2 * r3]
+ PIXEL_SSD_16x4
+ lea r0, [r0 + r6]
+ lea r2, [r2 + 2 * r3]
+ PIXEL_SSD_16x4
+ ret
+
+;-----------------------------------------------------------------------------
+; int pixel_ssd_48x64( uint8_t *, intptr_t, uint8_t *, intptr_t )
+;-----------------------------------------------------------------------------
+INIT_XMM sse4
+cglobal pixel_ssd_48x64, 4, 7, 8, src1, stride1, src2, stride2
+
+ pxor m7, m7
+ pxor m6, m6
+ mov r4, r0
+ mov r5, r2
+ lea r6, [r1 * 2]
+
+ call pixel_ssd_16x16_internal
+ lea r0, [r0 + r6]
+ lea r2, [r2 + 2 * r3]
+ call pixel_ssd_16x16_internal
+ lea r0, [r0 + r6]
+ lea r2, [r2 + 2 * r3]
+ call pixel_ssd_16x16_internal
+ lea r0, [r0 + r6]
+ lea r2, [r2 + 2 * r3]
+ call pixel_ssd_16x16_internal
+ lea r0, [r4 + 16]
+ lea r2, [r5 + 16]
+ call pixel_ssd_16x16_internal
+ lea r0, [r0 + r6]
+ lea r2, [r2 + 2 * r3]
+ call pixel_ssd_16x16_internal
+ lea r0, [r0 + r6]
+ lea r2, [r2 + 2 * r3]
+ call pixel_ssd_16x16_internal
+ lea r0, [r0 + r6]
+ lea r2, [r2 + 2 * r3]
+ call pixel_ssd_16x16_internal
+ lea r0, [r4 + 32]
+ lea r2, [r5 + 32]
+ call pixel_ssd_16x16_internal
+ lea r0, [r0 + r6]
+ lea r2, [r2 + 2 * r3]
+ call pixel_ssd_16x16_internal
+ lea r0, [r0 + r6]
+ lea r2, [r2 + 2 * r3]
+ call pixel_ssd_16x16_internal
+ lea r0, [r0 + r6]
+ lea r2, [r2 + 2 * r3]
+ call pixel_ssd_16x16_internal
+
+ HADDD m7, m1
+ movd eax, m7
+
+ RET
+
+;-----------------------------------------------------------------------------
+; int pixel_ssd_64x16( uint8_t *, intptr_t, uint8_t *, intptr_t )
+;-----------------------------------------------------------------------------
+INIT_XMM sse4
+cglobal pixel_ssd_64x16, 4, 7, 8, src1, stride1, src2, stride2
+
+ pxor m7, m7
+ pxor m6, m6
+ mov r4, r0
+ mov r5, r2
+ lea r6, [r1 * 2]
+
+ call pixel_ssd_16x16_internal
+ lea r0, [r4 + 16]
+ lea r2, [r5 + 16]
+ call pixel_ssd_16x16_internal
+ lea r0, [r4 + 32]
+ lea r2, [r5 + 32]
+ call pixel_ssd_16x16_internal
+ lea r0, [r4 + 48]
+ lea r2, [r5 + 48]
+ call pixel_ssd_16x16_internal
+
+ HADDD m7, m1
+ movd eax, m7
+
+ RET
+
;-----------------------------------------------------------------------------
; void pixel_ssd_nv12_core( uint16_t *pixuv1, intptr_t stride1, uint16_t *pixuv2, intptr_t stride2,
; int width, int height, uint64_t *ssd_u, uint64_t *ssd_v )
diff -r 81ecfb791aec -r 37238c6124be source/common/x86/pixel.h
--- a/source/common/x86/pixel.h Fri Nov 22 17:14:32 2013 +0530
+++ b/source/common/x86/pixel.h Fri Nov 22 17:39:55 2013 +0530
@@ -374,5 +374,7 @@
void x265_transpose64_sse2(pixel *dest, pixel *src, intptr_t stride);
int x265_pixel_ssd_12x16_sse4(pixel *, intptr_t, pixel *, intptr_t);
int x265_pixel_ssd_24x32_sse4(pixel *, intptr_t, pixel *, intptr_t);
+int x265_pixel_ssd_48x64_sse4(pixel *, intptr_t, pixel *, intptr_t);
+int x265_pixel_ssd_64x16_sse4(pixel *, intptr_t, pixel *, intptr_t);
#endif // ifndef X265_I386_PIXEL_H
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