[x265] [PATCH] asm: assembly code for pixel_sse_ss_32xN

[yuvaraj at multicorewareinc.com]

# HG changeset patch
# User Yuvaraj Venkatesh <yuvaraj at multicorewareinc.com>
# Date 1385387530 -19800
#      Mon Nov 25 19:22:10 2013 +0530
# Node ID 2ba2e95b57963f8c23412faaf7b73c4671fb8a10
# Parent  fea660d227b842c411240ff17297ddfbb738b540
asm: assembly code for pixel_sse_ss_32xN

diff -r fea660d227b8 -r 2ba2e95b5796 source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp	Mon Nov 25 18:54:32 2013 +0530
+++ b/source/common/x86/asm-primitives.cpp	Mon Nov 25 19:22:10 2013 +0530
@@ -102,6 +102,11 @@
     p.sse_ss[LUMA_16x16]   = x265_pixel_ssd_ss_16x16_ ## cpu; \
     p.sse_ss[LUMA_16x32]   = x265_pixel_ssd_ss_16x32_ ## cpu; \
     p.sse_ss[LUMA_16x64]   = x265_pixel_ssd_ss_16x64_ ## cpu; \
+    p.sse_ss[LUMA_32x8]   = x265_pixel_ssd_ss_32x8_ ## cpu; \
+    p.sse_ss[LUMA_32x16]   = x265_pixel_ssd_ss_32x16_ ## cpu; \
+    p.sse_ss[LUMA_32x24]   = x265_pixel_ssd_ss_32x24_ ## cpu; \
+    p.sse_ss[LUMA_32x32]   = x265_pixel_ssd_ss_32x32_ ## cpu; \
+    p.sse_ss[LUMA_32x64]   = x265_pixel_ssd_ss_32x64_ ## cpu;
 
 #define SA8D_INTER_FROM_BLOCK(cpu) \
     p.sa8d_inter[LUMA_4x8]  = x265_pixel_satd_4x8_ ## cpu; \
diff -r fea660d227b8 -r 2ba2e95b5796 source/common/x86/pixel-a.asm
--- a/source/common/x86/pixel-a.asm	Mon Nov 25 18:54:32 2013 +0530
+++ b/source/common/x86/pixel-a.asm	Mon Nov 25 19:22:10 2013 +0530
@@ -426,15 +426,124 @@
     RET
 %endmacro
 
+%macro SSD_SS_32 1
+cglobal pixel_ssd_ss_32x%1, 4,7,6
+    FIX_STRIDES r1, r3
+    mov    r4d, %1/2
+    pxor    m0, m0
+.loop
+    pmovsxwd  m1, [r0]
+    pmovsxwd  m2, [r2]
+    psubd     m1, m2
+    pmulld    m1, m1
+    paddd     m0, m1
+    pmovsxwd  m1, [r0 + 8]
+    pmovsxwd  m2, [r2 + 8]
+    psubd     m1, m2
+    pmulld    m1, m1
+    paddd     m0, m1
+    pmovsxwd  m1, [r0 + 16]
+    pmovsxwd  m2, [r2 + 16]
+    psubd     m1, m2
+    pmulld    m1, m1
+    paddd     m0, m1
+    pmovsxwd  m1, [r0 + 24]
+    pmovsxwd  m2, [r2 + 24]
+    psubd     m1, m2
+    pmulld    m1, m1
+    paddd     m0, m1
+    pmovsxwd  m1, [r0 + 32]
+    pmovsxwd  m2, [r2 + 32]
+    psubd     m1, m2
+    pmulld    m1, m1
+    paddd     m0, m1
+    pmovsxwd  m1, [r0 + 40]
+    pmovsxwd  m2, [r2 + 40]
+    psubd     m1, m2
+    pmulld    m1, m1
+    paddd     m0, m1
+    pmovsxwd  m1, [r0 + 48]
+    pmovsxwd  m2, [r2 + 48]
+    psubd     m1, m2
+    pmulld    m1, m1
+    paddd     m0, m1
+    pmovsxwd  m1, [r0 + 56]
+    pmovsxwd  m2, [r2 + 56]
+    psubd     m1, m2
+    pmulld    m1, m1
+    paddd     m0, m1
+    lea       r0, [r0 + 2*r1]
+    lea       r2, [r2 + 2*r3]
+    pmovsxwd  m1, [r0]
+    pmovsxwd  m2, [r2]
+    psubd     m1, m2
+    pmulld    m1, m1
+    paddd     m0, m1
+    pmovsxwd  m1, [r0 + 8]
+    pmovsxwd  m2, [r2 + 8]
+    psubd     m1, m2
+    pmulld    m1, m1
+    paddd     m0, m1
+    pmovsxwd  m1, [r0 + 16]
+    pmovsxwd  m2, [r2 + 16]
+    psubd     m1, m2
+    pmulld    m1, m1
+    paddd     m0, m1
+    pmovsxwd  m1, [r0 + 24]
+    pmovsxwd  m2, [r2 + 24]
+    psubd     m1, m2
+    pmulld    m1, m1
+    paddd     m0, m1
+    pmovsxwd  m1, [r0 + 32]
+    pmovsxwd  m2, [r2 + 32]
+    psubd     m1, m2
+    pmulld    m1, m1
+    paddd     m0, m1
+    pmovsxwd  m1, [r0 + 40]
+    pmovsxwd  m2, [r2 + 40]
+    psubd     m1, m2
+    pmulld    m1, m1
+    paddd     m0, m1
+    pmovsxwd  m1, [r0 + 48]
+    pmovsxwd  m2, [r2 + 48]
+    psubd     m1, m2
+    pmulld    m1, m1
+    paddd     m0, m1
+    pmovsxwd  m1, [r0 + 56]
+    pmovsxwd  m2, [r2 + 56]
+    psubd     m1, m2
+    pmulld    m1, m1
+    paddd     m0, m1
+    lea       r0, [r0 + 2*r1]
+    lea       r2, [r2 + 2*r3]
+    dec      r4d
+    jnz .loop
+    phaddd    m0, m0
+    phaddd    m0, m0
+    movd     eax, m0
+    RET
+%endmacro
+
+%macro SSD_SS_32xN 0
+SSD_SS_32 8
+SSD_SS_32 16
+SSD_SS_32 24
+SSD_SS_32 32
+SSD_SS_32 64
+%endmacro
+
 INIT_XMM sse2
 SSD_SS_ONE
 SSD_SS_12x16
+SSD_SS_32xN
 INIT_XMM sse4
 SSD_SS_ONE
 SSD_SS_12x16
+SSD_SS_32xN
 INIT_XMM avx
 SSD_SS_ONE
 SSD_SS_12x16
+SSD_SS_32xN
 %endif ; !HIGH_BIT_DEPTH
 
 %if HIGH_BIT_DEPTH == 0