[x265] [PATCH] asm: assembly code for pixel_sse_ss_24x32

[chen]

I check the encoder code again, I can't confirm [r0] is alignment pointer.
At 2013-11-26 21:59:46,yuvaraj at multicorewareinc.com wrote:
># HG changeset patch
># User Yuvaraj Venkatesh <yuvaraj at multicorewareinc.com>
># Date 1385474358 -19800
>#      Tue Nov 26 19:29:18 2013 +0530
># Node ID c82fab940f42d2d3ec1421f512e7237541257076
># Parent  491fd3ee6fd11a52f50ba22b39b9e9596b8e7238
>asm: assembly code for pixel_sse_ss_24x32
>
>diff -r 491fd3ee6fd1 -r c82fab940f42 source/common/x86/asm-primitives.cpp
>--- a/source/common/x86/asm-primitives.cpp	Mon Nov 25 14:00:56 2013 -0600
>+++ b/source/common/x86/asm-primitives.cpp	Tue Nov 26 19:29:18 2013 +0530
>@@ -103,6 +103,7 @@
>     p.sse_ss[LUMA_16x16]   = x265_pixel_ssd_ss_16x16_ ## cpu; \
>     p.sse_ss[LUMA_16x32]   = x265_pixel_ssd_ss_16x32_ ## cpu; \
>     p.sse_ss[LUMA_16x64]   = x265_pixel_ssd_ss_16x64_ ## cpu; \
>+    p.sse_ss[LUMA_24x32]   = x265_pixel_ssd_ss_24x32_ ## cpu; \
>     p.sse_ss[LUMA_32x8]   = x265_pixel_ssd_ss_32x8_ ## cpu; \
>     p.sse_ss[LUMA_32x16]   = x265_pixel_ssd_ss_32x16_ ## cpu; \
>     p.sse_ss[LUMA_32x24]   = x265_pixel_ssd_ss_32x24_ ## cpu; \
>diff -r 491fd3ee6fd1 -r c82fab940f42 source/common/x86/pixel-a.asm
>--- a/source/common/x86/pixel-a.asm	Mon Nov 25 14:00:56 2013 -0600
>+++ b/source/common/x86/pixel-a.asm	Tue Nov 26 19:29:18 2013 +0530
>@@ -469,17 +469,68 @@
> SSD_SS_32 64
> %endmacro
> 
>+%macro SSD_SS_24 0
>+cglobal pixel_ssd_ss_24x32, 4,7,6
>+    FIX_STRIDES r1, r3
>+    mov    r4d, 16
>+    pxor    m0, m0
>+.loop
>+    mova    m1, [r0]
>+    movu    m2, [r2]
>+    psubw   m1, m2
>+    pmaddwd m1, m1
>+    paddd   m0, m1
>+    mova    m1, [r0 + 16]
>+    movu    m2, [r2 + 16]
>+    psubw   m1, m2
>+    pmaddwd m1, m1
>+    paddd   m0, m1
>+    mova    m1, [r0 + 32]
>+    movu    m2, [r2 + 32]
>+    psubw   m1, m2
>+    pmaddwd m1, m1
>+    paddd   m0, m1
>+    lea       r0, [r0 + 2*r1]
>+    lea       r2, [r2 + 2*r3]
>+    mova    m1, [r0]
>+    movu    m2, [r2]
>+    psubw   m1, m2
>+    pmaddwd m1, m1
>+    paddd   m0, m1
>+    mova    m1, [r0 + 16]
>+    movu    m2, [r2 + 16]
>+    psubw   m1, m2
>+    pmaddwd m1, m1
>+    paddd   m0, m1
>+    mova    m1, [r0 + 32]
>+    movu    m2, [r2 + 32]
>+    psubw   m1, m2
>+    pmaddwd m1, m1
>+    paddd   m0, m1
>+    lea       r0, [r0 + 2*r1]
>+    lea       r2, [r2 + 2*r3]
>+    dec      r4d
>+    jnz .loop
>+    phaddd    m0, m0
>+    phaddd    m0, m0
>+    movd     eax, m0
>+    RET
>+%endmacro
>+
> INIT_XMM sse2
> SSD_SS_ONE
> SSD_SS_12x16
>+SSD_SS_24
> SSD_SS_32xN
> INIT_XMM sse4
> SSD_SS_ONE
> SSD_SS_12x16
>+SSD_SS_24
> SSD_SS_32xN
> INIT_XMM avx
> SSD_SS_ONE
> SSD_SS_12x16
>+SSD_SS_24
> SSD_SS_32xN
> %endif ; !HIGH_BIT_DEPTH
> 
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