[x265] [PATCH] asm: code for pixel_sse_sp_64xN
murugan at multicorewareinc.com
murugan at multicorewareinc.com
Wed Nov 27 11:54:30 CET 2013
# HG changeset patch
# User Murugan Vairavel <murugan at multicorewareinc.com>
# Date 1385549585 -19800
# Wed Nov 27 16:23:05 2013 +0530
# Branch stable
# Node ID 7078582cea0ba56fbaf24dc9041f0d1aa66ac46a
# Parent 82d78c197e42614e4c580841c81bfc23aa47ccc8
asm: code for pixel_sse_sp_64xN
diff -r 82d78c197e42 -r 7078582cea0b source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Wed Nov 27 16:21:08 2013 +0530
+++ b/source/common/x86/asm-primitives.cpp Wed Nov 27 16:23:05 2013 +0530
@@ -653,6 +653,10 @@
p.sse_sp[LUMA_32x32] = x265_pixel_ssd_sp_32x32_sse4;
p.sse_sp[LUMA_32x64] = x265_pixel_ssd_sp_32x64_sse4;
p.sse_sp[LUMA_48x64] = x265_pixel_ssd_sp_48x64_sse4;
+ p.sse_sp[LUMA_64x16] = x265_pixel_ssd_sp_64x16_sse4;
+ p.sse_sp[LUMA_64x32] = x265_pixel_ssd_sp_64x32_sse4;
+ p.sse_sp[LUMA_64x48] = x265_pixel_ssd_sp_64x48_sse4;
+ p.sse_sp[LUMA_64x64] = x265_pixel_ssd_sp_64x64_sse4;
CHROMA_PIXELSUB_PS(_sse4);
diff -r 82d78c197e42 -r 7078582cea0b source/common/x86/pixel-a.asm
--- a/source/common/x86/pixel-a.asm Wed Nov 27 16:21:08 2013 +0530
+++ b/source/common/x86/pixel-a.asm Wed Nov 27 16:23:05 2013 +0530
@@ -1605,6 +1605,182 @@
RET
;-----------------------------------------------------------------------------
+; int pixel_ssd_64x16( uint8_t *, intptr_t, uint8_t *, intptr_t )
+;-----------------------------------------------------------------------------
+INIT_XMM sse4
+cglobal pixel_ssd_sp_64x16, 4, 7, 8, src1, stride1, src2, stride2
+
+ pxor m7, m7
+ pxor m6, m6
+ mov r5, r0
+ mov r6, r2
+ add r1, r1
+ lea r4, [r1 * 2]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r5 + 32]
+ lea r2, [r6 + 16]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r5 + 64]
+ lea r2, [r6 + 32]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r5 + 96]
+ lea r2, [r6 + 48]
+ call pixel_ssd_sp_16x16_internal
+ HADDD m7, m1
+ movd eax, m7
+ RET
+
+;-----------------------------------------------------------------------------
+; int pixel_ssd_64x32( uint8_t *, intptr_t, uint8_t *, intptr_t )
+;-----------------------------------------------------------------------------
+INIT_XMM sse4
+cglobal pixel_ssd_sp_64x32, 4, 7, 8, src1, stride1, src2, stride2
+
+ pxor m7, m7
+ pxor m6, m6
+ mov r5, r0
+ mov r6, r2
+ add r1, r1
+ lea r4, [r1 * 2]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r0 + r4]
+ lea r2, [r2 + 2 * r3]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r5 + 32]
+ lea r2, [r6 + 16]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r0 + r4]
+ lea r2, [r2 + 2 * r3]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r5 + 64]
+ lea r2, [r6 + 32]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r0 + r4]
+ lea r2, [r2 + 2 * r3]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r5 + 96]
+ lea r2, [r6 + 48]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r0 + r4]
+ lea r2, [r2 + 2 * r3]
+ call pixel_ssd_sp_16x16_internal
+ HADDD m7, m1
+ movd eax, m7
+ RET
+
+;-----------------------------------------------------------------------------
+; int pixel_ssd_64x48( uint8_t *, intptr_t, uint8_t *, intptr_t )
+;-----------------------------------------------------------------------------
+INIT_XMM sse4
+cglobal pixel_ssd_sp_64x48, 4, 7, 8, src1, stride1, src2, stride2
+
+ pxor m7, m7
+ pxor m6, m6
+ mov r5, r0
+ mov r6, r2
+ add r1, r1
+ lea r4, [r1 * 2]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r0 + r4]
+ lea r2, [r2 + 2 * r3]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r0 + r4]
+ lea r2, [r2 + 2 * r3]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r5 + 32]
+ lea r2, [r6 + 16]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r0 + r4]
+ lea r2, [r2 + 2 * r3]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r0 + r4]
+ lea r2, [r2 + 2 * r3]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r5 + 64]
+ lea r2, [r6 + 32]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r0 + r4]
+ lea r2, [r2 + 2 * r3]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r0 + r4]
+ lea r2, [r2 + 2 * r3]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r5 + 96]
+ lea r2, [r6 + 48]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r0 + r4]
+ lea r2, [r2 + 2 * r3]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r0 + r4]
+ lea r2, [r2 + 2 * r3]
+ call pixel_ssd_sp_16x16_internal
+ HADDD m7, m1
+ movd eax, m7
+ RET
+
+;-----------------------------------------------------------------------------
+; int pixel_ssd_64x64( uint8_t *, intptr_t, uint8_t *, intptr_t )
+;-----------------------------------------------------------------------------
+INIT_XMM sse4
+cglobal pixel_ssd_sp_64x64, 4, 7, 8, src1, stride1, src2, stride2
+
+ pxor m7, m7
+ pxor m6, m6
+ mov r5, r0
+ mov r6, r2
+ add r1, r1
+ lea r4, [r1 * 2]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r0 + r4]
+ lea r2, [r2 + 2 * r3]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r0 + r4]
+ lea r2, [r2 + 2 * r3]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r0 + r4]
+ lea r2, [r2 + 2 * r3]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r5 + 32]
+ lea r2, [r6 + 16]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r0 + r4]
+ lea r2, [r2 + 2 * r3]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r0 + r4]
+ lea r2, [r2 + 2 * r3]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r0 + r4]
+ lea r2, [r2 + 2 * r3]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r5 + 64]
+ lea r2, [r6 + 32]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r0 + r4]
+ lea r2, [r2 + 2 * r3]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r0 + r4]
+ lea r2, [r2 + 2 * r3]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r0 + r4]
+ lea r2, [r2 + 2 * r3]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r5 + 96]
+ lea r2, [r6 + 48]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r0 + r4]
+ lea r2, [r2 + 2 * r3]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r0 + r4]
+ lea r2, [r2 + 2 * r3]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r0 + r4]
+ lea r2, [r2 + 2 * r3]
+ call pixel_ssd_sp_16x16_internal
+ HADDD m7, m1
+ movd eax, m7
+ RET
+
+;-----------------------------------------------------------------------------
; void pixel_ssd_nv12_core( uint16_t *pixuv1, intptr_t stride1, uint16_t *pixuv2, intptr_t stride2,
; int width, int height, uint64_t *ssd_u, uint64_t *ssd_v )
;
diff -r 82d78c197e42 -r 7078582cea0b source/common/x86/pixel.h
--- a/source/common/x86/pixel.h Wed Nov 27 16:21:08 2013 +0530
+++ b/source/common/x86/pixel.h Wed Nov 27 16:23:05 2013 +0530
@@ -413,4 +413,8 @@
int x265_pixel_ssd_sp_32x32_sse4(int16_t *, intptr_t, pixel *, intptr_t);
int x265_pixel_ssd_sp_32x64_sse4(int16_t *, intptr_t, pixel *, intptr_t);
int x265_pixel_ssd_sp_48x64_sse4(int16_t *, intptr_t, pixel *, intptr_t);
+int x265_pixel_ssd_sp_64x16_sse4(int16_t *, intptr_t, pixel *, intptr_t);
+int x265_pixel_ssd_sp_64x32_sse4(int16_t *, intptr_t, pixel *, intptr_t);
+int x265_pixel_ssd_sp_64x48_sse4(int16_t *, intptr_t, pixel *, intptr_t);
+int x265_pixel_ssd_sp_64x64_sse4(int16_t *, intptr_t, pixel *, intptr_t);
#endif // ifndef X265_I386_PIXEL_H
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