[x265] [PATCH] replace sad_x3_12 vector class function with intrinsic
dnyaneshwar at multicorewareinc.com
dnyaneshwar at multicorewareinc.com
Thu Oct 3 16:16:27 CEST 2013
# HG changeset patch
# User Dnyaneshwar
# Date 1380809737 -19800
# Thu Oct 03 19:45:37 2013 +0530
# Node ID adeb4daba79fa52ae0171dc8d4b1dd4218e7d2f9
# Parent 76d82811cd42e019fb8e23e99804a240f6382c44
replace sad_x3_12 vector class function with intrinsic.
diff -r 76d82811cd42 -r adeb4daba79f source/common/vec/pixel8.inc
--- a/source/common/vec/pixel8.inc Thu Oct 03 19:41:55 2013 +0530
+++ b/source/common/vec/pixel8.inc Thu Oct 03 19:45:37 2013 +0530
@@ -3814,81 +3814,810 @@
#endif /* if HAVE_MMX */
-#endif /* if INSTRSET >= X265_CPU_LEVEL_SSE41 */
-
/* For performance - This function assumes that the *last load* can access 16 elements. */
-template<int ly>
-void sad_x3_12(pixel *fenc, pixel *fref1, pixel *fref2, pixel *fref3, intptr_t frefstride, int *res)
-{
- Vec16uc m1, n1, n2, n3;
-
- Vec4i sum1(0), sum2(0), sum3(0);
- Vec8us sad1(0), sad2(0), sad3(0);
- int max_iterators = (ly >> 4) << 4;
- int row;
-
- for (row = 0; row < max_iterators; row += 16)
- {
- for (int i = 0; i < 16; i++)
- {
- m1.load_a(fenc);
- m1.cutoff(12);
- n1.load(fref1);
- n1.cutoff(12);
- n2.load(fref2);
- n2.cutoff(12);
- n3.load(fref3);
- n3.cutoff(12);
-
- sad1.addSumAbsDiff(m1, n1);
- sad2.addSumAbsDiff(m1, n2);
- sad3.addSumAbsDiff(m1, n3);
-
- fenc += FENC_STRIDE;
- fref1 += frefstride;
- fref2 += frefstride;
- fref3 += frefstride;
- }
-
- sum1 += extend_low(sad1) + extend_high(sad1);
- sum2 += extend_low(sad2) + extend_high(sad2);
- sum3 += extend_low(sad3) + extend_high(sad3);
- sad1 = 0;
- sad2 = 0;
- sad3 = 0;
- }
-
- while (row++ < ly)
- {
- m1.load_a(fenc);
- m1.cutoff(12);
- n1.load(fref1);
- n1.cutoff(12);
- n2.load(fref2);
- n2.cutoff(12);
- n3.load(fref3);
- n3.cutoff(12);
-
- sad1.addSumAbsDiff(m1, n1);
- sad2.addSumAbsDiff(m1, n2);
- sad3.addSumAbsDiff(m1, n3);
-
- fenc += FENC_STRIDE;
- fref1 += frefstride;
- fref2 += frefstride;
- fref3 += frefstride;
- }
-
- sum1 += extend_low(sad1) + extend_high(sad1);
- sum2 += extend_low(sad2) + extend_high(sad2);
- sum3 += extend_low(sad3) + extend_high(sad3);
-
- res[0] = horizontal_add(sum1);
- res[1] = horizontal_add(sum2);
- res[2] = horizontal_add(sum3);
+
+template<int ly>
+void sad_x3_12(pixel *fenc, pixel *fref1, pixel *fref2, pixel *fref3, intptr_t frefstride, int *res)
+{
+ assert((ly % 4) == 0);
+
+ __m128i mask = _mm_set_epi32(0x0, 0xffffffff, 0xffffffff, 0xffffffff);
+
+ if(ly == 4)
+ {
+ __m128i T00, T01, T02, T03;
+ __m128i T10, T11, T12, T13;
+ __m128i T20, T21, T22, T23;
+ __m128i sum0, sum1;
+
+ T00 = _mm_load_si128((__m128i*)(fenc));
+ T00 = _mm_and_si128(T00, mask);
+ T01 = _mm_load_si128((__m128i*)(fenc + FENC_STRIDE));
+ T01 = _mm_and_si128(T01, mask);
+ T02 = _mm_load_si128((__m128i*)(fenc + (2) * FENC_STRIDE));
+ T02 = _mm_and_si128(T02, mask);
+ T03 = _mm_load_si128((__m128i*)(fenc + (3) * FENC_STRIDE));
+ T03 = _mm_and_si128(T03, mask);
+
+ T10 = _mm_loadu_si128((__m128i*)(fref1));
+ T10 = _mm_and_si128(T10, mask);
+ T11 = _mm_loadu_si128((__m128i*)(fref1 + frefstride));
+ T11 = _mm_and_si128(T11, mask);
+ T12 = _mm_loadu_si128((__m128i*)(fref1 + (2) * frefstride));
+ T12 = _mm_and_si128(T12, mask);
+ T13 = _mm_loadu_si128((__m128i*)(fref1 + (3) * frefstride));
+ T13 = _mm_and_si128(T13, mask);
+
+ T20 = _mm_sad_epu8(T00, T10);
+ T21 = _mm_sad_epu8(T01, T11);
+ T22 = _mm_sad_epu8(T02, T12);
+ T23 = _mm_sad_epu8(T03, T13);
+
+ T20 = _mm_add_epi16(T20, T21);
+ T22 = _mm_add_epi16(T22, T23);
+ sum0 = _mm_add_epi16(T20, T22);
+
+ sum1 = _mm_shuffle_epi32(sum0, 2);
+ sum0 = _mm_add_epi32(sum0, sum1);
+ res[0] = _mm_cvtsi128_si32(sum0);
+
+ T10 = _mm_loadu_si128((__m128i*)(fref2));
+ T10 = _mm_and_si128(T10, mask);
+ T11 = _mm_loadu_si128((__m128i*)(fref2 + frefstride));
+ T11 = _mm_and_si128(T11, mask);
+ T12 = _mm_loadu_si128((__m128i*)(fref2 + (2) * frefstride));
+ T12 = _mm_and_si128(T12, mask);
+ T13 = _mm_loadu_si128((__m128i*)(fref2 + (3) * frefstride));
+ T13 = _mm_and_si128(T13, mask);
+
+ T20 = _mm_sad_epu8(T00, T10);
+ T21 = _mm_sad_epu8(T01, T11);
+ T22 = _mm_sad_epu8(T02, T12);
+ T23 = _mm_sad_epu8(T03, T13);
+
+ T20 = _mm_add_epi16(T20, T21);
+ T22 = _mm_add_epi16(T22, T23);
+ sum0 = _mm_add_epi16(T20, T22);
+
+ sum1 = _mm_shuffle_epi32(sum0, 2);
+ sum0 = _mm_add_epi32(sum0, sum1);
+ res[1] = _mm_cvtsi128_si32(sum0);
+
+ T10 = _mm_loadu_si128((__m128i*)(fref3));
+ T10 = _mm_and_si128(T10, mask);
+ T11 = _mm_loadu_si128((__m128i*)(fref3 + frefstride));
+ T11 = _mm_and_si128(T11, mask);
+ T12 = _mm_loadu_si128((__m128i*)(fref3 + (2) * frefstride));
+ T12 = _mm_and_si128(T12, mask);
+ T13 = _mm_loadu_si128((__m128i*)(fref3 + (3) * frefstride));
+ T13 = _mm_and_si128(T13, mask);
+
+ T20 = _mm_sad_epu8(T00, T10);
+ T21 = _mm_sad_epu8(T01, T11);
+ T22 = _mm_sad_epu8(T02, T12);
+ T23 = _mm_sad_epu8(T03, T13);
+
+ T20 = _mm_add_epi16(T20, T21);
+ T22 = _mm_add_epi16(T22, T23);
+ sum0 = _mm_add_epi16(T20, T22);
+
+ sum1 = _mm_shuffle_epi32(sum0, 2);
+ sum0 = _mm_add_epi32(sum0, sum1);
+ res[2] = _mm_cvtsi128_si32(sum0);
+ }
+ if (ly == 8)
+ {
+ __m128i T00, T01, T02, T03;
+ __m128i T10, T11, T12, T13;
+ __m128i T20, T21, T22, T23;
+ __m128i sum0, sum1;
+
+ T00 = _mm_load_si128((__m128i*)(fenc));
+ T00 = _mm_and_si128(T00, mask);
+ T01 = _mm_load_si128((__m128i*)(fenc + FENC_STRIDE));
+ T01 = _mm_and_si128(T01, mask);
+ T02 = _mm_load_si128((__m128i*)(fenc + (2) * FENC_STRIDE));
+ T02 = _mm_and_si128(T02, mask);
+ T03 = _mm_load_si128((__m128i*)(fenc + (3) * FENC_STRIDE));
+ T03 = _mm_and_si128(T03, mask);
+
+ T10 = _mm_loadu_si128((__m128i*)(fref1));
+ T10 = _mm_and_si128(T10, mask);
+ T11 = _mm_loadu_si128((__m128i*)(fref1 + frefstride));
+ T11 = _mm_and_si128(T11, mask);
+ T12 = _mm_loadu_si128((__m128i*)(fref1 + (2) * frefstride));
+ T12 = _mm_and_si128(T12, mask);
+ T13 = _mm_loadu_si128((__m128i*)(fref1 + (3) * frefstride));
+ T13 = _mm_and_si128(T13, mask);
+
+ T20 = _mm_sad_epu8(T00, T10);
+ T21 = _mm_sad_epu8(T01, T11);
+ T22 = _mm_sad_epu8(T02, T12);
+ T23 = _mm_sad_epu8(T03, T13);
+
+ T20 = _mm_add_epi16(T20, T21);
+ T22 = _mm_add_epi16(T22, T23);
+ sum0 = _mm_add_epi16(T20, T22);
+
+ sum1 = _mm_shuffle_epi32(sum0, 2);
+ sum0 = _mm_add_epi32(sum0, sum1);
+ res[0] = _mm_cvtsi128_si32(sum0);
+
+ T10 = _mm_loadu_si128((__m128i*)(fref2));
+ T10 = _mm_and_si128(T10, mask);
+ T11 = _mm_loadu_si128((__m128i*)(fref2 + frefstride));
+ T11 = _mm_and_si128(T11, mask);
+ T12 = _mm_loadu_si128((__m128i*)(fref2 + (2) * frefstride));
+ T12 = _mm_and_si128(T12, mask);
+ T13 = _mm_loadu_si128((__m128i*)(fref2 + (3) * frefstride));
+ T13 = _mm_and_si128(T13, mask);
+
+ T20 = _mm_sad_epu8(T00, T10);
+ T21 = _mm_sad_epu8(T01, T11);
+ T22 = _mm_sad_epu8(T02, T12);
+ T23 = _mm_sad_epu8(T03, T13);
+
+ T20 = _mm_add_epi16(T20, T21);
+ T22 = _mm_add_epi16(T22, T23);
+ sum0 = _mm_add_epi16(T20, T22);
+
+ sum1 = _mm_shuffle_epi32(sum0, 2);
+ sum0 = _mm_add_epi32(sum0, sum1);
+ res[1] = _mm_cvtsi128_si32(sum0);
+
+ T10 = _mm_loadu_si128((__m128i*)(fref3));
+ T10 = _mm_and_si128(T10, mask);
+ T11 = _mm_loadu_si128((__m128i*)(fref3 + frefstride));
+ T11 = _mm_and_si128(T11, mask);
+ T12 = _mm_loadu_si128((__m128i*)(fref3 + (2) * frefstride));
+ T12 = _mm_and_si128(T12, mask);
+ T13 = _mm_loadu_si128((__m128i*)(fref3 + (3) * frefstride));
+ T13 = _mm_and_si128(T13, mask);
+
+ T20 = _mm_sad_epu8(T00, T10);
+ T21 = _mm_sad_epu8(T01, T11);
+ T22 = _mm_sad_epu8(T02, T12);
+ T23 = _mm_sad_epu8(T03, T13);
+
+ T20 = _mm_add_epi16(T20, T21);
+ T22 = _mm_add_epi16(T22, T23);
+ sum0 = _mm_add_epi16(T20, T22);
+
+ sum1 = _mm_shuffle_epi32(sum0, 2);
+ sum0 = _mm_add_epi32(sum0, sum1);
+ res[2] = _mm_cvtsi128_si32(sum0);
+
+ T00 = _mm_load_si128((__m128i*)(fenc + (4) * FENC_STRIDE));
+ T00 = _mm_and_si128(T00, mask);
+ T01 = _mm_load_si128((__m128i*)(fenc + (5) * FENC_STRIDE));
+ T01 = _mm_and_si128(T01, mask);
+ T02 = _mm_load_si128((__m128i*)(fenc + (6) * FENC_STRIDE));
+ T02 = _mm_and_si128(T02, mask);
+ T03 = _mm_load_si128((__m128i*)(fenc + (7) * FENC_STRIDE));
+ T03 = _mm_and_si128(T03, mask);
+
+ T10 = _mm_loadu_si128((__m128i*)(fref1 + (4) * frefstride));
+ T10 = _mm_and_si128(T10, mask);
+ T11 = _mm_loadu_si128((__m128i*)(fref1 + (5) * frefstride));
+ T11 = _mm_and_si128(T11, mask);
+ T12 = _mm_loadu_si128((__m128i*)(fref1 + (6) * frefstride));
+ T12 = _mm_and_si128(T12, mask);
+ T13 = _mm_loadu_si128((__m128i*)(fref1 + (7) * frefstride));
+ T13 = _mm_and_si128(T13, mask);
+
+ T20 = _mm_sad_epu8(T00, T10);
+ T21 = _mm_sad_epu8(T01, T11);
+ T22 = _mm_sad_epu8(T02, T12);
+ T23 = _mm_sad_epu8(T03, T13);
+
+ T20 = _mm_add_epi16(T20, T21);
+ T22 = _mm_add_epi16(T22, T23);
+ sum0 = _mm_add_epi16(T20, T22);
+
+ sum1 = _mm_shuffle_epi32(sum0, 2);
+ sum0 = _mm_add_epi32(sum0, sum1);
+ res[0] += _mm_cvtsi128_si32(sum0);
+
+ T10 = _mm_loadu_si128((__m128i*)(fref2 + (4) * frefstride));
+ T10 = _mm_and_si128(T10, mask);
+ T11 = _mm_loadu_si128((__m128i*)(fref2 + (5) * frefstride));
+ T11 = _mm_and_si128(T11, mask);
+ T12 = _mm_loadu_si128((__m128i*)(fref2 + (6) * frefstride));
+ T12 = _mm_and_si128(T12, mask);
+ T13 = _mm_loadu_si128((__m128i*)(fref2 + (7) * frefstride));
+ T13 = _mm_and_si128(T13, mask);
+
+ T20 = _mm_sad_epu8(T00, T10);
+ T21 = _mm_sad_epu8(T01, T11);
+ T22 = _mm_sad_epu8(T02, T12);
+ T23 = _mm_sad_epu8(T03, T13);
+
+ T20 = _mm_add_epi16(T20, T21);
+ T22 = _mm_add_epi16(T22, T23);
+ sum0 = _mm_add_epi16(T20, T22);
+
+ sum1 = _mm_shuffle_epi32(sum0, 2);
+ sum0 = _mm_add_epi32(sum0, sum1);
+ res[1] += _mm_cvtsi128_si32(sum0);
+
+ T10 = _mm_loadu_si128((__m128i*)(fref3 + (4) * frefstride));
+ T10 = _mm_and_si128(T10, mask);
+ T11 = _mm_loadu_si128((__m128i*)(fref3 + (5) * frefstride));
+ T11 = _mm_and_si128(T11, mask);
+ T12 = _mm_loadu_si128((__m128i*)(fref3 + (6) * frefstride));
+ T12 = _mm_and_si128(T12, mask);
+ T13 = _mm_loadu_si128((__m128i*)(fref3 + (7) * frefstride));
+ T13 = _mm_and_si128(T13, mask);
+
+ T20 = _mm_sad_epu8(T00, T10);
+ T21 = _mm_sad_epu8(T01, T11);
+ T22 = _mm_sad_epu8(T02, T12);
+ T23 = _mm_sad_epu8(T03, T13);
+
+ T20 = _mm_add_epi16(T20, T21);
+ T22 = _mm_add_epi16(T22, T23);
+ sum0 = _mm_add_epi16(T20, T22);
+
+ sum1 = _mm_shuffle_epi32(sum0, 2);
+ sum0 = _mm_add_epi32(sum0, sum1);
+ res[2] += _mm_cvtsi128_si32(sum0);
+ }
+ if (ly == 16)
+ {
+ __m128i T00, T01, T02, T03;
+ __m128i T10, T11, T12, T13;
+ __m128i T20, T21, T22, T23;
+ __m128i sum0, sum1;
+
+ T00 = _mm_load_si128((__m128i*)(fenc));
+ T00 = _mm_and_si128(T00, mask);
+ T01 = _mm_load_si128((__m128i*)(fenc + FENC_STRIDE));
+ T01 = _mm_and_si128(T01, mask);
+ T02 = _mm_load_si128((__m128i*)(fenc + (2) * FENC_STRIDE));
+ T02 = _mm_and_si128(T02, mask);
+ T03 = _mm_load_si128((__m128i*)(fenc + (3) * FENC_STRIDE));
+ T03 = _mm_and_si128(T03, mask);
+
+ T10 = _mm_loadu_si128((__m128i*)(fref1));
+ T10 = _mm_and_si128(T10, mask);
+ T11 = _mm_loadu_si128((__m128i*)(fref1 + frefstride));
+ T11 = _mm_and_si128(T11, mask);
+ T12 = _mm_loadu_si128((__m128i*)(fref1 + (2) * frefstride));
+ T12 = _mm_and_si128(T12, mask);
+ T13 = _mm_loadu_si128((__m128i*)(fref1 + (3) * frefstride));
+ T13 = _mm_and_si128(T13, mask);
+
+ T20 = _mm_sad_epu8(T00, T10);
+ T21 = _mm_sad_epu8(T01, T11);
+ T22 = _mm_sad_epu8(T02, T12);
+ T23 = _mm_sad_epu8(T03, T13);
+
+ T20 = _mm_add_epi16(T20, T21);
+ T22 = _mm_add_epi16(T22, T23);
+ sum0 = _mm_add_epi16(T20, T22);
+
+ sum1 = _mm_shuffle_epi32(sum0, 2);
+ sum0 = _mm_add_epi32(sum0, sum1);
+ res[0] = _mm_cvtsi128_si32(sum0);
+
+ T10 = _mm_loadu_si128((__m128i*)(fref2));
+ T10 = _mm_and_si128(T10, mask);
+ T11 = _mm_loadu_si128((__m128i*)(fref2 + frefstride));
+ T11 = _mm_and_si128(T11, mask);
+ T12 = _mm_loadu_si128((__m128i*)(fref2 + (2) * frefstride));
+ T12 = _mm_and_si128(T12, mask);
+ T13 = _mm_loadu_si128((__m128i*)(fref2 + (3) * frefstride));
+ T13 = _mm_and_si128(T13, mask);
+
+ T20 = _mm_sad_epu8(T00, T10);
+ T21 = _mm_sad_epu8(T01, T11);
+ T22 = _mm_sad_epu8(T02, T12);
+ T23 = _mm_sad_epu8(T03, T13);
+
+ T20 = _mm_add_epi16(T20, T21);
+ T22 = _mm_add_epi16(T22, T23);
+ sum0 = _mm_add_epi16(T20, T22);
+
+ sum1 = _mm_shuffle_epi32(sum0, 2);
+ sum0 = _mm_add_epi32(sum0, sum1);
+ res[1] = _mm_cvtsi128_si32(sum0);
+
+ T10 = _mm_loadu_si128((__m128i*)(fref3));
+ T10 = _mm_and_si128(T10, mask);
+ T11 = _mm_loadu_si128((__m128i*)(fref3 + frefstride));
+ T11 = _mm_and_si128(T11, mask);
+ T12 = _mm_loadu_si128((__m128i*)(fref3 + (2) * frefstride));
+ T12 = _mm_and_si128(T12, mask);
+ T13 = _mm_loadu_si128((__m128i*)(fref3 + (3) * frefstride));
+ T13 = _mm_and_si128(T13, mask);
+
+ T20 = _mm_sad_epu8(T00, T10);
+ T21 = _mm_sad_epu8(T01, T11);
+ T22 = _mm_sad_epu8(T02, T12);
+ T23 = _mm_sad_epu8(T03, T13);
+
+ T20 = _mm_add_epi16(T20, T21);
+ T22 = _mm_add_epi16(T22, T23);
+ sum0 = _mm_add_epi16(T20, T22);
+
+ sum1 = _mm_shuffle_epi32(sum0, 2);
+ sum0 = _mm_add_epi32(sum0, sum1);
+ res[2] = _mm_cvtsi128_si32(sum0);
+
+ T00 = _mm_load_si128((__m128i*)(fenc + (4) * FENC_STRIDE));
+ T00 = _mm_and_si128(T00, mask);
+ T01 = _mm_load_si128((__m128i*)(fenc + (5) * FENC_STRIDE));
+ T01 = _mm_and_si128(T01, mask);
+ T02 = _mm_load_si128((__m128i*)(fenc + (6) * FENC_STRIDE));
+ T02 = _mm_and_si128(T02, mask);
+ T03 = _mm_load_si128((__m128i*)(fenc + (7) * FENC_STRIDE));
+ T03 = _mm_and_si128(T03, mask);
+
+ T10 = _mm_loadu_si128((__m128i*)(fref1 + (4) * frefstride));
+ T10 = _mm_and_si128(T10, mask);
+ T11 = _mm_loadu_si128((__m128i*)(fref1 + (5) * frefstride));
+ T11 = _mm_and_si128(T11, mask);
+ T12 = _mm_loadu_si128((__m128i*)(fref1 + (6) * frefstride));
+ T12 = _mm_and_si128(T12, mask);
+ T13 = _mm_loadu_si128((__m128i*)(fref1 + (7) * frefstride));
+ T13 = _mm_and_si128(T13, mask);
+
+ T20 = _mm_sad_epu8(T00, T10);
+ T21 = _mm_sad_epu8(T01, T11);
+ T22 = _mm_sad_epu8(T02, T12);
+ T23 = _mm_sad_epu8(T03, T13);
+
+ T20 = _mm_add_epi16(T20, T21);
+ T22 = _mm_add_epi16(T22, T23);
+ sum0 = _mm_add_epi16(T20, T22);
+
+ sum1 = _mm_shuffle_epi32(sum0, 2);
+ sum0 = _mm_add_epi32(sum0, sum1);
+ res[0] += _mm_cvtsi128_si32(sum0);
+
+ T10 = _mm_loadu_si128((__m128i*)(fref2 + (4) * frefstride));
+ T10 = _mm_and_si128(T10, mask);
+ T11 = _mm_loadu_si128((__m128i*)(fref2 + (5) * frefstride));
+ T11 = _mm_and_si128(T11, mask);
+ T12 = _mm_loadu_si128((__m128i*)(fref2 + (6) * frefstride));
+ T12 = _mm_and_si128(T12, mask);
+ T13 = _mm_loadu_si128((__m128i*)(fref2 + (7) * frefstride));
+ T13 = _mm_and_si128(T13, mask);
+
+ T20 = _mm_sad_epu8(T00, T10);
+ T21 = _mm_sad_epu8(T01, T11);
+ T22 = _mm_sad_epu8(T02, T12);
+ T23 = _mm_sad_epu8(T03, T13);
+
+ T20 = _mm_add_epi16(T20, T21);
+ T22 = _mm_add_epi16(T22, T23);
+ sum0 = _mm_add_epi16(T20, T22);
+
+ sum1 = _mm_shuffle_epi32(sum0, 2);
+ sum0 = _mm_add_epi32(sum0, sum1);
+ res[1] += _mm_cvtsi128_si32(sum0);
+
+ T10 = _mm_loadu_si128((__m128i*)(fref3 + (4) * frefstride));
+ T10 = _mm_and_si128(T10, mask);
+ T11 = _mm_loadu_si128((__m128i*)(fref3 + (5) * frefstride));
+ T11 = _mm_and_si128(T11, mask);
+ T12 = _mm_loadu_si128((__m128i*)(fref3 + (6) * frefstride));
+ T12 = _mm_and_si128(T12, mask);
+ T13 = _mm_loadu_si128((__m128i*)(fref3 + (7) * frefstride));
+ T13 = _mm_and_si128(T13, mask);
+
+ T20 = _mm_sad_epu8(T00, T10);
+ T21 = _mm_sad_epu8(T01, T11);
+ T22 = _mm_sad_epu8(T02, T12);
+ T23 = _mm_sad_epu8(T03, T13);
+
+ T20 = _mm_add_epi16(T20, T21);
+ T22 = _mm_add_epi16(T22, T23);
+ sum0 = _mm_add_epi16(T20, T22);
+
+ sum1 = _mm_shuffle_epi32(sum0, 2);
+ sum0 = _mm_add_epi32(sum0, sum1);
+ res[2] += _mm_cvtsi128_si32(sum0);
+
+ T00 = _mm_load_si128((__m128i*)(fenc + (8) * FENC_STRIDE));
+ T00 = _mm_and_si128(T00, mask);
+ T01 = _mm_load_si128((__m128i*)(fenc + (9) * FENC_STRIDE));
+ T01 = _mm_and_si128(T01, mask);
+ T02 = _mm_load_si128((__m128i*)(fenc + (10) * FENC_STRIDE));
+ T02 = _mm_and_si128(T02, mask);
+ T03 = _mm_load_si128((__m128i*)(fenc + (11) * FENC_STRIDE));
+ T03 = _mm_and_si128(T03, mask);
+
+ T10 = _mm_loadu_si128((__m128i*)(fref1 + (8) * frefstride));
+ T10 = _mm_and_si128(T10, mask);
+ T11 = _mm_loadu_si128((__m128i*)(fref1 + (9) * frefstride));
+ T11 = _mm_and_si128(T11, mask);
+ T12 = _mm_loadu_si128((__m128i*)(fref1 + (10) * frefstride));
+ T12 = _mm_and_si128(T12, mask);
+ T13 = _mm_loadu_si128((__m128i*)(fref1 + (11) * frefstride));
+ T13 = _mm_and_si128(T13, mask);
+
+ T20 = _mm_sad_epu8(T00, T10);
+ T21 = _mm_sad_epu8(T01, T11);
+ T22 = _mm_sad_epu8(T02, T12);
+ T23 = _mm_sad_epu8(T03, T13);
+
+ T20 = _mm_add_epi16(T20, T21);
+ T22 = _mm_add_epi16(T22, T23);
+ sum0 = _mm_add_epi16(T20, T22);
+
+ sum1 = _mm_shuffle_epi32(sum0, 2);
+ sum0 = _mm_add_epi32(sum0, sum1);
+ res[0] += _mm_cvtsi128_si32(sum0);
+
+ T10 = _mm_loadu_si128((__m128i*)(fref2 + (8) * frefstride));
+ T10 = _mm_and_si128(T10, mask);
+ T11 = _mm_loadu_si128((__m128i*)(fref2 + (9) * frefstride));
+ T11 = _mm_and_si128(T11, mask);
+ T12 = _mm_loadu_si128((__m128i*)(fref2 + (10) * frefstride));
+ T12 = _mm_and_si128(T12, mask);
+ T13 = _mm_loadu_si128((__m128i*)(fref2 + (11) * frefstride));
+ T13 = _mm_and_si128(T13, mask);
+
+ T20 = _mm_sad_epu8(T00, T10);
+ T21 = _mm_sad_epu8(T01, T11);
+ T22 = _mm_sad_epu8(T02, T12);
+ T23 = _mm_sad_epu8(T03, T13);
+
+ T20 = _mm_add_epi16(T20, T21);
+ T22 = _mm_add_epi16(T22, T23);
+ sum0 = _mm_add_epi16(T20, T22);
+
+ sum1 = _mm_shuffle_epi32(sum0, 2);
+ sum0 = _mm_add_epi32(sum0, sum1);
+ res[1] += _mm_cvtsi128_si32(sum0);
+
+ T10 = _mm_loadu_si128((__m128i*)(fref3 + (8) * frefstride));
+ T10 = _mm_and_si128(T10, mask);
+ T11 = _mm_loadu_si128((__m128i*)(fref3 + (9) * frefstride));
+ T11 = _mm_and_si128(T11, mask);
+ T12 = _mm_loadu_si128((__m128i*)(fref3 + (10) * frefstride));
+ T12 = _mm_and_si128(T12, mask);
+ T13 = _mm_loadu_si128((__m128i*)(fref3 + (11) * frefstride));
+ T13 = _mm_and_si128(T13, mask);
+
+ T20 = _mm_sad_epu8(T00, T10);
+ T21 = _mm_sad_epu8(T01, T11);
+ T22 = _mm_sad_epu8(T02, T12);
+ T23 = _mm_sad_epu8(T03, T13);
+
+ T20 = _mm_add_epi16(T20, T21);
+ T22 = _mm_add_epi16(T22, T23);
+ sum0 = _mm_add_epi16(T20, T22);
+
+ sum1 = _mm_shuffle_epi32(sum0, 2);
+ sum0 = _mm_add_epi32(sum0, sum1);
+ res[2] += _mm_cvtsi128_si32(sum0);
+
+ T00 = _mm_load_si128((__m128i*)(fenc + (12) * FENC_STRIDE));
+ T00 = _mm_and_si128(T00, mask);
+ T01 = _mm_load_si128((__m128i*)(fenc + (13) * FENC_STRIDE));
+ T01 = _mm_and_si128(T01, mask);
+ T02 = _mm_load_si128((__m128i*)(fenc + (14) * FENC_STRIDE));
+ T02 = _mm_and_si128(T02, mask);
+ T03 = _mm_load_si128((__m128i*)(fenc + (15) * FENC_STRIDE));
+ T03 = _mm_and_si128(T03, mask);
+
+ T10 = _mm_loadu_si128((__m128i*)(fref1 + (12) * frefstride));
+ T10 = _mm_and_si128(T10, mask);
+ T11 = _mm_loadu_si128((__m128i*)(fref1 + (13) * frefstride));
+ T11 = _mm_and_si128(T11, mask);
+ T12 = _mm_loadu_si128((__m128i*)(fref1 + (14) * frefstride));
+ T12 = _mm_and_si128(T12, mask);
+ T13 = _mm_loadu_si128((__m128i*)(fref1 + (15) * frefstride));
+ T13 = _mm_and_si128(T13, mask);
+
+ T20 = _mm_sad_epu8(T00, T10);
+ T21 = _mm_sad_epu8(T01, T11);
+ T22 = _mm_sad_epu8(T02, T12);
+ T23 = _mm_sad_epu8(T03, T13);
+
+ T20 = _mm_add_epi16(T20, T21);
+ T22 = _mm_add_epi16(T22, T23);
+ sum0 = _mm_add_epi16(T20, T22);
+
+ sum1 = _mm_shuffle_epi32(sum0, 2);
+ sum0 = _mm_add_epi32(sum0, sum1);
+ res[0] += _mm_cvtsi128_si32(sum0);
+
+ T10 = _mm_loadu_si128((__m128i*)(fref2 + (12) * frefstride));
+ T10 = _mm_and_si128(T10, mask);
+ T11 = _mm_loadu_si128((__m128i*)(fref2 + (13) * frefstride));
+ T11 = _mm_and_si128(T11, mask);
+ T12 = _mm_loadu_si128((__m128i*)(fref2 + (14) * frefstride));
+ T12 = _mm_and_si128(T12, mask);
+ T13 = _mm_loadu_si128((__m128i*)(fref2 + (15) * frefstride));
+ T13 = _mm_and_si128(T13, mask);
+
+ T20 = _mm_sad_epu8(T00, T10);
+ T21 = _mm_sad_epu8(T01, T11);
+ T22 = _mm_sad_epu8(T02, T12);
+ T23 = _mm_sad_epu8(T03, T13);
+
+ T20 = _mm_add_epi16(T20, T21);
+ T22 = _mm_add_epi16(T22, T23);
+ sum0 = _mm_add_epi16(T20, T22);
+
+ sum1 = _mm_shuffle_epi32(sum0, 2);
+ sum0 = _mm_add_epi32(sum0, sum1);
+ res[1] += _mm_cvtsi128_si32(sum0);
+
+ T10 = _mm_loadu_si128((__m128i*)(fref3 + (12) * frefstride));
+ T10 = _mm_and_si128(T10, mask);
+ T11 = _mm_loadu_si128((__m128i*)(fref3 + (13) * frefstride));
+ T11 = _mm_and_si128(T11, mask);
+ T12 = _mm_loadu_si128((__m128i*)(fref3 + (14) * frefstride));
+ T12 = _mm_and_si128(T12, mask);
+ T13 = _mm_loadu_si128((__m128i*)(fref3 + (15) * frefstride));
+ T13 = _mm_and_si128(T13, mask);
+
+ T20 = _mm_sad_epu8(T00, T10);
+ T21 = _mm_sad_epu8(T01, T11);
+ T22 = _mm_sad_epu8(T02, T12);
+ T23 = _mm_sad_epu8(T03, T13);
+
+ T20 = _mm_add_epi16(T20, T21);
+ T22 = _mm_add_epi16(T22, T23);
+ sum0 = _mm_add_epi16(T20, T22);
+
+ sum1 = _mm_shuffle_epi32(sum0, 2);
+ sum0 = _mm_add_epi32(sum0, sum1);
+ res[2] += _mm_cvtsi128_si32(sum0);
+ }
+ if ((ly % 8) == 0)
+ {
+ res[0] = res[1] = res[2] = 0;
+ for(int i = 0; i < ly; i += 8)
+ {
+ __m128i T00, T01, T02, T03;
+ __m128i T10, T11, T12, T13;
+ __m128i T20, T21, T22, T23;
+ __m128i sum0, sum1;
+
+ T00 = _mm_load_si128((__m128i*)(fenc + (i) * FENC_STRIDE));
+ T00 = _mm_and_si128(T00, mask);
+ T01 = _mm_load_si128((__m128i*)(fenc + (i + 1) * FENC_STRIDE));
+ T01 = _mm_and_si128(T01, mask);
+ T02 = _mm_load_si128((__m128i*)(fenc + (i + 2) * FENC_STRIDE));
+ T02 = _mm_and_si128(T02, mask);
+ T03 = _mm_load_si128((__m128i*)(fenc + (i + 3) * FENC_STRIDE));
+ T03 = _mm_and_si128(T03, mask);
+
+ T10 = _mm_loadu_si128((__m128i*)(fref1 + (i) * frefstride));
+ T10 = _mm_and_si128(T10, mask);
+ T11 = _mm_loadu_si128((__m128i*)(fref1 + (i + 1) * frefstride));
+ T11 = _mm_and_si128(T11, mask);
+ T12 = _mm_loadu_si128((__m128i*)(fref1 + (i + 2) * frefstride));
+ T12 = _mm_and_si128(T12, mask);
+ T13 = _mm_loadu_si128((__m128i*)(fref1 + (i + 3) * frefstride));
+ T13 = _mm_and_si128(T13, mask);
+
+ T20 = _mm_sad_epu8(T00, T10);
+ T21 = _mm_sad_epu8(T01, T11);
+ T22 = _mm_sad_epu8(T02, T12);
+ T23 = _mm_sad_epu8(T03, T13);
+
+ T20 = _mm_add_epi16(T20, T21);
+ T22 = _mm_add_epi16(T22, T23);
+ sum0 = _mm_add_epi16(T20, T22);
+
+ sum1 = _mm_shuffle_epi32(sum0, 2);
+ sum0 = _mm_add_epi32(sum0, sum1);
+ res[0] += _mm_cvtsi128_si32(sum0);
+
+ T10 = _mm_loadu_si128((__m128i*)(fref2 + (i) * frefstride));
+ T10 = _mm_and_si128(T10, mask);
+ T11 = _mm_loadu_si128((__m128i*)(fref2 + (i + 1) * frefstride));
+ T11 = _mm_and_si128(T11, mask);
+ T12 = _mm_loadu_si128((__m128i*)(fref2 + (i + 2) * frefstride));
+ T12 = _mm_and_si128(T12, mask);
+ T13 = _mm_loadu_si128((__m128i*)(fref2 + (i + 3) * frefstride));
+ T13 = _mm_and_si128(T13, mask);
+
+ T20 = _mm_sad_epu8(T00, T10);
+ T21 = _mm_sad_epu8(T01, T11);
+ T22 = _mm_sad_epu8(T02, T12);
+ T23 = _mm_sad_epu8(T03, T13);
+
+ T20 = _mm_add_epi16(T20, T21);
+ T22 = _mm_add_epi16(T22, T23);
+ sum0 = _mm_add_epi16(T20, T22);
+
+ sum1 = _mm_shuffle_epi32(sum0, 2);
+ sum0 = _mm_add_epi32(sum0, sum1);
+ res[1] += _mm_cvtsi128_si32(sum0);
+
+ T10 = _mm_loadu_si128((__m128i*)(fref3 + (i) * frefstride));
+ T10 = _mm_and_si128(T10, mask);
+ T11 = _mm_loadu_si128((__m128i*)(fref3 + (i + 1) * frefstride));
+ T11 = _mm_and_si128(T11, mask);
+ T12 = _mm_loadu_si128((__m128i*)(fref3 + (i + 2) * frefstride));
+ T12 = _mm_and_si128(T12, mask);
+ T13 = _mm_loadu_si128((__m128i*)(fref3 + (i + 3) * frefstride));
+ T13 = _mm_and_si128(T13, mask);
+
+ T20 = _mm_sad_epu8(T00, T10);
+ T21 = _mm_sad_epu8(T01, T11);
+ T22 = _mm_sad_epu8(T02, T12);
+ T23 = _mm_sad_epu8(T03, T13);
+
+ T20 = _mm_add_epi16(T20, T21);
+ T22 = _mm_add_epi16(T22, T23);
+ sum0 = _mm_add_epi16(T20, T22);
+
+ sum1 = _mm_shuffle_epi32(sum0, 2);
+ sum0 = _mm_add_epi32(sum0, sum1);
+ res[2] += _mm_cvtsi128_si32(sum0);
+
+ T00 = _mm_load_si128((__m128i*)(fenc + (i + 4) * FENC_STRIDE));
+ T00 = _mm_and_si128(T00, mask);
+ T01 = _mm_load_si128((__m128i*)(fenc + (i + 5) * FENC_STRIDE));
+ T01 = _mm_and_si128(T01, mask);
+ T02 = _mm_load_si128((__m128i*)(fenc + (i + 6) * FENC_STRIDE));
+ T02 = _mm_and_si128(T02, mask);
+ T03 = _mm_load_si128((__m128i*)(fenc + (i + 7) * FENC_STRIDE));
+ T03 = _mm_and_si128(T03, mask);
+
+ T10 = _mm_loadu_si128((__m128i*)(fref1 + (i + 4) * frefstride));
+ T10 = _mm_and_si128(T10, mask);
+ T11 = _mm_loadu_si128((__m128i*)(fref1 + (i + 5) * frefstride));
+ T11 = _mm_and_si128(T11, mask);
+ T12 = _mm_loadu_si128((__m128i*)(fref1 + (i + 6) * frefstride));
+ T12 = _mm_and_si128(T12, mask);
+ T13 = _mm_loadu_si128((__m128i*)(fref1 + (i + 7) * frefstride));
+ T13 = _mm_and_si128(T13, mask);
+
+ T20 = _mm_sad_epu8(T00, T10);
+ T21 = _mm_sad_epu8(T01, T11);
+ T22 = _mm_sad_epu8(T02, T12);
+ T23 = _mm_sad_epu8(T03, T13);
+
+ T20 = _mm_add_epi16(T20, T21);
+ T22 = _mm_add_epi16(T22, T23);
+ sum0 = _mm_add_epi16(T20, T22);
+
+ sum1 = _mm_shuffle_epi32(sum0, 2);
+ sum0 = _mm_add_epi32(sum0, sum1);
+ res[0] += _mm_cvtsi128_si32(sum0);
+
+ T10 = _mm_loadu_si128((__m128i*)(fref2 + (i + 4) * frefstride));
+ T10 = _mm_and_si128(T10, mask);
+ T11 = _mm_loadu_si128((__m128i*)(fref2 + (i + 5) * frefstride));
+ T11 = _mm_and_si128(T11, mask);
+ T12 = _mm_loadu_si128((__m128i*)(fref2 + (i + 6) * frefstride));
+ T12 = _mm_and_si128(T12, mask);
+ T13 = _mm_loadu_si128((__m128i*)(fref2 + (i + 7) * frefstride));
+ T13 = _mm_and_si128(T13, mask);
+
+ T20 = _mm_sad_epu8(T00, T10);
+ T21 = _mm_sad_epu8(T01, T11);
+ T22 = _mm_sad_epu8(T02, T12);
+ T23 = _mm_sad_epu8(T03, T13);
+
+ T20 = _mm_add_epi16(T20, T21);
+ T22 = _mm_add_epi16(T22, T23);
+ sum0 = _mm_add_epi16(T20, T22);
+
+ sum1 = _mm_shuffle_epi32(sum0, 2);
+ sum0 = _mm_add_epi32(sum0, sum1);
+ res[1] += _mm_cvtsi128_si32(sum0);
+
+ T10 = _mm_loadu_si128((__m128i*)(fref3 + (i + 4) * frefstride));
+ T10 = _mm_and_si128(T10, mask);
+ T11 = _mm_loadu_si128((__m128i*)(fref3 + (i + 5) * frefstride));
+ T11 = _mm_and_si128(T11, mask);
+ T12 = _mm_loadu_si128((__m128i*)(fref3 + (i + 6) * frefstride));
+ T12 = _mm_and_si128(T12, mask);
+ T13 = _mm_loadu_si128((__m128i*)(fref3 + (i + 7) * frefstride));
+ T13 = _mm_and_si128(T13, mask);
+
+ T20 = _mm_sad_epu8(T00, T10);
+ T21 = _mm_sad_epu8(T01, T11);
+ T22 = _mm_sad_epu8(T02, T12);
+ T23 = _mm_sad_epu8(T03, T13);
+
+ T20 = _mm_add_epi16(T20, T21);
+ T22 = _mm_add_epi16(T22, T23);
+ sum0 = _mm_add_epi16(T20, T22);
+
+ sum1 = _mm_shuffle_epi32(sum0, 2);
+ sum0 = _mm_add_epi32(sum0, sum1);
+ res[2] += _mm_cvtsi128_si32(sum0);
+ }
+ }
+ else
+ {
+ res[0] = res[1] = res[2] = 0;
+ for(int i = 0; i < ly; i += 4)
+ {
+ __m128i T00, T01, T02, T03;
+ __m128i T10, T11, T12, T13;
+ __m128i T20, T21, T22, T23;
+ __m128i sum0, sum1;
+
+ T00 = _mm_load_si128((__m128i*)(fenc + (i) * FENC_STRIDE));
+ T00 = _mm_and_si128(T00, mask);
+ T01 = _mm_load_si128((__m128i*)(fenc + (i + 1) * FENC_STRIDE));
+ T01 = _mm_and_si128(T01, mask);
+ T02 = _mm_load_si128((__m128i*)(fenc + (i + 2) * FENC_STRIDE));
+ T02 = _mm_and_si128(T02, mask);
+ T03 = _mm_load_si128((__m128i*)(fenc + (i + 3) * FENC_STRIDE));
+ T03 = _mm_and_si128(T03, mask);
+
+ T10 = _mm_loadu_si128((__m128i*)(fref1 + (i) * frefstride));
+ T10 = _mm_and_si128(T10, mask);
+ T11 = _mm_loadu_si128((__m128i*)(fref1 + (i + 1) * frefstride));
+ T11 = _mm_and_si128(T11, mask);
+ T12 = _mm_loadu_si128((__m128i*)(fref1 + (i + 2) * frefstride));
+ T12 = _mm_and_si128(T12, mask);
+ T13 = _mm_loadu_si128((__m128i*)(fref1 + (i + 3) * frefstride));
+ T13 = _mm_and_si128(T13, mask);
+
+ T20 = _mm_sad_epu8(T00, T10);
+ T21 = _mm_sad_epu8(T01, T11);
+ T22 = _mm_sad_epu8(T02, T12);
+ T23 = _mm_sad_epu8(T03, T13);
+
+ T20 = _mm_add_epi16(T20, T21);
+ T22 = _mm_add_epi16(T22, T23);
+ sum0 = _mm_add_epi16(T20, T22);
+
+ sum1 = _mm_shuffle_epi32(sum0, 2);
+ sum0 = _mm_add_epi32(sum0, sum1);
+ res[0] += _mm_cvtsi128_si32(sum0);
+
+ T10 = _mm_loadu_si128((__m128i*)(fref2 + (i) * frefstride));
+ T10 = _mm_and_si128(T10, mask);
+ T11 = _mm_loadu_si128((__m128i*)(fref2 + (i + 1) * frefstride));
+ T11 = _mm_and_si128(T11, mask);
+ T12 = _mm_loadu_si128((__m128i*)(fref2 + (i + 2) * frefstride));
+ T12 = _mm_and_si128(T12, mask);
+ T13 = _mm_loadu_si128((__m128i*)(fref2 + (i + 3) * frefstride));
+ T13 = _mm_and_si128(T13, mask);
+
+ T20 = _mm_sad_epu8(T00, T10);
+ T21 = _mm_sad_epu8(T01, T11);
+ T22 = _mm_sad_epu8(T02, T12);
+ T23 = _mm_sad_epu8(T03, T13);
+
+ T20 = _mm_add_epi16(T20, T21);
+ T22 = _mm_add_epi16(T22, T23);
+ sum0 = _mm_add_epi16(T20, T22);
+
+ sum1 = _mm_shuffle_epi32(sum0, 2);
+ sum0 = _mm_add_epi32(sum0, sum1);
+ res[1] += _mm_cvtsi128_si32(sum0);
+
+ T10 = _mm_loadu_si128((__m128i*)(fref3 + (i) * frefstride));
+ T10 = _mm_and_si128(T10, mask);
+ T11 = _mm_loadu_si128((__m128i*)(fref3 + (i + 1) * frefstride));
+ T11 = _mm_and_si128(T11, mask);
+ T12 = _mm_loadu_si128((__m128i*)(fref3 + (i + 2) * frefstride));
+ T12 = _mm_and_si128(T12, mask);
+ T13 = _mm_loadu_si128((__m128i*)(fref3 + (i + 3) * frefstride));
+ T13 = _mm_and_si128(T13, mask);
+
+ T20 = _mm_sad_epu8(T00, T10);
+ T21 = _mm_sad_epu8(T01, T11);
+ T22 = _mm_sad_epu8(T02, T12);
+ T23 = _mm_sad_epu8(T03, T13);
+
+ T20 = _mm_add_epi16(T20, T21);
+ T22 = _mm_add_epi16(T22, T23);
+ sum0 = _mm_add_epi16(T20, T22);
+
+ sum1 = _mm_shuffle_epi32(sum0, 2);
+ sum0 = _mm_add_epi32(sum0, sum1);
+ res[2] += _mm_cvtsi128_si32(sum0);
+ }
+ }
}
-#if INSTRSET >= X265_CPU_LEVEL_SSE41
template<int ly>
void sad_x3_16(pixel *fenc, pixel *fref1, pixel *fref2, pixel *fref3, intptr_t frefstride, int *res)
{
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