[x265] [PATCH Review Only] filterHorizontal_p_p_4, for 4x4 block
praveen at multicorewareinc.com
praveen at multicorewareinc.com
Fri Oct 4 14:49:06 CEST 2013
# HG changeset patch
# User praveen Tiwari
# Date 1380890893 -19800
# Node ID f1b84f51c6ca4bff034f8a6422ac66dc31b7825c
# Parent bf14f75b8cf99806c75cdc1a50b28b6cf265e3bd
filterHorizontal_p_p_4, for 4x4 block
diff -r bf14f75b8cf9 -r f1b84f51c6ca source/common/x86/ipfilter8.asm
--- a/source/common/x86/ipfilter8.asm Fri Oct 04 01:39:22 2013 -0500
+++ b/source/common/x86/ipfilter8.asm Fri Oct 04 18:18:13 2013 +0530
@@ -26,107 +26,58 @@
%include "x86inc.asm"
%include "x86util.asm"
-%if ARCH_X86_64 == 0
-
SECTION_RODATA 32
-tab_leftmask: db -1, -1, -1, -1, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0
-
tab_Tm: db 0, 1, 2, 3, 1, 2, 3, 4, 2, 3, 4, 5, 3, 4, 5, 6
- db 4, 5, 6, 7, 5, 6, 7, 8, 6, 7, 8, 9, 7, 8, 9, 10
tab_c_512: times 8 dw 512
SECTION .text
-%macro FILTER_H4 3
- movu %1, [src + col - 1]
- pshufb %2, %1, Tm4
+%macro FILTER_H4_w4 3
+ movu %1, [srcq - 1]
+ pshufb %2, %1, Tm0
pmaddubsw %2, coef2
- pshufb %1, %1, Tm5
- pmaddubsw %1, coef2
phaddw %2, %1
pmulhrsw %2, %3
packuswb %2, %2
%endmacro
+%macro FILTER_H4_w4_CALL 0
+ FILTER_H4_w4 x0, x1, x2
+
+ movd [dstq], x1
+
+ add srcq, srcstrideq
+ add dstq, dststrideq
+%endmacro
+
;-----------------------------------------------------------------------------
; void filterHorizontal_p_p_4(pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int width, int height, short const *coeff)
;-----------------------------------------------------------------------------
INIT_XMM sse4
-cglobal filterHorizontal_p_p_4, 0, 7, 8
-%define src r0
-%define dst r1
-%define row r2
-%define col r3
-%define width r4
-%define widthleft r5
-%define mask_offset r6
-%define coef2 m7
-%define x3 m6
-%define Tm5 m5
-%define Tm4 m4
-%define x2 m3
-%define x1 m2
-%define x0 m1
-%define leftmask m0
-%define tmp r0
-%define tmp1 r1
-
- mov tmp, r6m
- movu coef2, [tmp]
+cglobal filterHorizontal_p_p_4, 4, 5, 5, src, srcstride, dst, dststride
+%define coef2 m4
+%define Tm0 m3
+%define x2 m2
+%define x1 m1
+%define x0 m0
+
+ mov r4, r6m
+ movu coef2, [r4]
packsswb coef2, coef2
pshufd coef2, coef2, 0
- mova x3, [tab_c_512]
+ mova x2, [tab_c_512]
- mov width, r4m
- mov widthleft, width
- and width, ~7
- and widthleft, 7
- mov mask_offset, widthleft
- neg mask_offset
+ mova Tm0, [tab_Tm]
- movq leftmask, [tab_leftmask + (7 + mask_offset)]
- mova Tm4, [tab_Tm]
- mova Tm5, [tab_Tm + 16]
+%rep 3
+FILTER_H4_w4_CALL
+%endrep
- mov src, r0m
- mov dst, r2m
- mov row, r5m
-
-_loop_row:
- xor col, col
-
-_loop_col:
- FILTER_H4 x0, x1, x3
- movh [dst + col], x1
-
- add col, 8
-
- cmp col, width
- jl _loop_col
-
-_end_col:
- test widthleft, widthleft
- jz _next_row
-
- movq x2, [dst + col]
- FILTER_H4 x0, x1, x3
- pblendvb x2, x2, x1, leftmask
- movh [dst + col], x2
-
-_next_row:
- add src, r1m
- add dst, r3m
- dec row
-
- test row, row
- jz _end_row
-
- jmp _loop_row
+ FILTER_H4_w4 x0, x1, x2
+ movd [dstq], x1
_end_row:
RET
-
-%endif ; ARCH_X86_64 == 0
More information about the x265-devel
mailing list