[x265] [PATCH] pixel: simplify sad_x3_32 to make it easier to maintain
dnyaneshwar at multicorewareinc.com
dnyaneshwar at multicorewareinc.com
Mon Oct 7 12:20:18 CEST 2013
# HG changeset patch
# User Dnyaneshwar Gorade <dnyaneshwar at multicorewareinc.com>
# Date 1381141165 -19800
# Mon Oct 07 15:49:25 2013 +0530
# Node ID f09b76fd12be1c6fee5672463b965010b1a08170
# Parent 53d922d7822f03400ebf4c7688b61d0f4b5d2057
pixel: simplify sad_x3_32 to make it easier to maintain
diff -r 53d922d7822f -r f09b76fd12be source/common/vec/pixel-sse41.cpp
--- a/source/common/vec/pixel-sse41.cpp Mon Oct 07 15:39:31 2013 +0530
+++ b/source/common/vec/pixel-sse41.cpp Mon Oct 07 15:49:25 2013 +0530
@@ -1621,236 +1621,103 @@
void sad_x3_32(pixel *fenc, pixel *fref1, pixel *fref2, pixel *fref3, intptr_t frefstride, int *res)
{
res[0] = res[1] = res[2] = 0;
+ __m128i T00, T01, T02, T03, T04, T05, T06, T07;
+ __m128i T10, T11, T12, T13, T14, T15, T16, T17;
+ __m128i T20, T21, T22, T23, T24, T25, T26, T27;
+ __m128i sum0, sum1;
+
+#define PROCESS_32x4x3(BASE) \
+ T00 = _mm_load_si128((__m128i*)(fenc + (BASE) * FENC_STRIDE)); \
+ T01 = _mm_load_si128((__m128i*)(fenc + (BASE + 1) * FENC_STRIDE)); \
+ T02 = _mm_load_si128((__m128i*)(fenc + (BASE + 2) * FENC_STRIDE)); \
+ T03 = _mm_load_si128((__m128i*)(fenc + (BASE + 3) * FENC_STRIDE)); \
+ T04 = _mm_load_si128((__m128i*)(fenc + (BASE) * FENC_STRIDE + 16)); \
+ T05 = _mm_load_si128((__m128i*)(fenc + (BASE + 1) * FENC_STRIDE + 16)); \
+ T06 = _mm_load_si128((__m128i*)(fenc + (BASE + 2) * FENC_STRIDE + 16)); \
+ T07 = _mm_load_si128((__m128i*)(fenc + (BASE + 3) * FENC_STRIDE + 16)); \
+ T10 = _mm_loadu_si128((__m128i*)(fref1 + (BASE) * frefstride)); \
+ T11 = _mm_loadu_si128((__m128i*)(fref1 + (BASE + 1) * frefstride)); \
+ T12 = _mm_loadu_si128((__m128i*)(fref1 + (BASE + 2) * frefstride)); \
+ T13 = _mm_loadu_si128((__m128i*)(fref1 + (BASE + 3) * frefstride)); \
+ T14 = _mm_loadu_si128((__m128i*)(fref1 + (BASE) * frefstride + 16)); \
+ T15 = _mm_loadu_si128((__m128i*)(fref1 + (BASE + 1) * frefstride + 16)); \
+ T16 = _mm_loadu_si128((__m128i*)(fref1 + (BASE + 2) * frefstride + 16)); \
+ T17 = _mm_loadu_si128((__m128i*)(fref1 + (BASE + 3) * frefstride + 16)); \
+ T20 = _mm_sad_epu8(T00, T10); \
+ T21 = _mm_sad_epu8(T01, T11); \
+ T22 = _mm_sad_epu8(T02, T12); \
+ T23 = _mm_sad_epu8(T03, T13); \
+ T24 = _mm_sad_epu8(T04, T14); \
+ T25 = _mm_sad_epu8(T05, T15); \
+ T26 = _mm_sad_epu8(T06, T16); \
+ T27 = _mm_sad_epu8(T07, T17); \
+ T20 = _mm_add_epi16(T20, T21); \
+ T22 = _mm_add_epi16(T22, T23); \
+ T24 = _mm_add_epi16(T24, T25); \
+ T26 = _mm_add_epi16(T26, T27); \
+ sum0 = _mm_add_epi16(T20, T22); \
+ sum0 = _mm_add_epi16(sum0, T24); \
+ sum0 = _mm_add_epi16(sum0, T26); \
+ sum1 = _mm_shuffle_epi32(sum0, 2); \
+ sum0 = _mm_add_epi32(sum0, sum1); \
+ res[0] += _mm_cvtsi128_si32(sum0); \
+ T10 = _mm_loadu_si128((__m128i*)(fref2 + (BASE) * frefstride)); \
+ T11 = _mm_loadu_si128((__m128i*)(fref2 + (BASE + 1) * frefstride)); \
+ T12 = _mm_loadu_si128((__m128i*)(fref2 + (BASE + 2) * frefstride)); \
+ T13 = _mm_loadu_si128((__m128i*)(fref2 + (BASE + 3) * frefstride)); \
+ T14 = _mm_loadu_si128((__m128i*)(fref2 + (BASE) * frefstride + 16)); \
+ T15 = _mm_loadu_si128((__m128i*)(fref2 + (BASE + 1) * frefstride + 16)); \
+ T16 = _mm_loadu_si128((__m128i*)(fref2 + (BASE + 2) * frefstride + 16)); \
+ T17 = _mm_loadu_si128((__m128i*)(fref2 + (BASE + 3) * frefstride + 16)); \
+ T20 = _mm_sad_epu8(T00, T10); \
+ T21 = _mm_sad_epu8(T01, T11); \
+ T22 = _mm_sad_epu8(T02, T12); \
+ T23 = _mm_sad_epu8(T03, T13); \
+ T24 = _mm_sad_epu8(T04, T14); \
+ T25 = _mm_sad_epu8(T05, T15); \
+ T26 = _mm_sad_epu8(T06, T16); \
+ T27 = _mm_sad_epu8(T07, T17); \
+ T20 = _mm_add_epi16(T20, T21); \
+ T22 = _mm_add_epi16(T22, T23); \
+ T24 = _mm_add_epi16(T24, T25); \
+ T26 = _mm_add_epi16(T26, T27); \
+ sum0 = _mm_add_epi16(T20, T22); \
+ sum0 = _mm_add_epi16(sum0, T24); \
+ sum0 = _mm_add_epi16(sum0, T26); \
+ sum1 = _mm_shuffle_epi32(sum0, 2); \
+ sum0 = _mm_add_epi32(sum0, sum1); \
+ res[1] += _mm_cvtsi128_si32(sum0); \
+ T10 = _mm_loadu_si128((__m128i*)(fref3 + (BASE) * frefstride)); \
+ T11 = _mm_loadu_si128((__m128i*)(fref3 + (BASE + 1) * frefstride)); \
+ T12 = _mm_loadu_si128((__m128i*)(fref3 + (BASE + 2) * frefstride)); \
+ T13 = _mm_loadu_si128((__m128i*)(fref3 + (BASE + 3) * frefstride)); \
+ T14 = _mm_loadu_si128((__m128i*)(fref3 + (BASE) * frefstride + 16)); \
+ T15 = _mm_loadu_si128((__m128i*)(fref3 + (BASE + 1) * frefstride + 16)); \
+ T16 = _mm_loadu_si128((__m128i*)(fref3 + (BASE + 2) * frefstride + 16)); \
+ T17 = _mm_loadu_si128((__m128i*)(fref3 + (BASE + 3) * frefstride + 16)); \
+ T20 = _mm_sad_epu8(T00, T10); \
+ T21 = _mm_sad_epu8(T01, T11); \
+ T22 = _mm_sad_epu8(T02, T12); \
+ T23 = _mm_sad_epu8(T03, T13); \
+ T24 = _mm_sad_epu8(T04, T14); \
+ T25 = _mm_sad_epu8(T05, T15); \
+ T26 = _mm_sad_epu8(T06, T16); \
+ T27 = _mm_sad_epu8(T07, T17); \
+ T20 = _mm_add_epi16(T20, T21); \
+ T22 = _mm_add_epi16(T22, T23); \
+ T24 = _mm_add_epi16(T24, T25); \
+ T26 = _mm_add_epi16(T26, T27); \
+ sum0 = _mm_add_epi16(T20, T22); \
+ sum0 = _mm_add_epi16(sum0, T24); \
+ sum0 = _mm_add_epi16(sum0, T26); \
+ sum1 = _mm_shuffle_epi32(sum0, 2); \
+ sum0 = _mm_add_epi32(sum0, sum1); \
+ res[2] += _mm_cvtsi128_si32(sum0);
+
for(int i = 0; i < ly; i += 8)
{
- __m128i T00, T01, T02, T03, T04, T05, T06, T07;
- __m128i T10, T11, T12, T13, T14, T15, T16, T17;
- __m128i T20, T21, T22, T23, T24, T25, T26, T27;
- __m128i sum0, sum1;
-
- T00 = _mm_load_si128((__m128i*)(fenc + (i) * FENC_STRIDE));
- T01 = _mm_load_si128((__m128i*)(fenc + (i + 1) * FENC_STRIDE));
- T02 = _mm_load_si128((__m128i*)(fenc + (i + 2) * FENC_STRIDE));
- T03 = _mm_load_si128((__m128i*)(fenc + (i + 3) * FENC_STRIDE));
-
- T04 = _mm_load_si128((__m128i*)(fenc + (i) * FENC_STRIDE + 16));
- T05 = _mm_load_si128((__m128i*)(fenc + (i + 1) * FENC_STRIDE + 16));
- T06 = _mm_load_si128((__m128i*)(fenc + (i + 2) * FENC_STRIDE + 16));
- T07 = _mm_load_si128((__m128i*)(fenc + (i + 3) * FENC_STRIDE + 16));
-
- T10 = _mm_loadu_si128((__m128i*)(fref1 + (i) * frefstride));
- T11 = _mm_loadu_si128((__m128i*)(fref1 + (i + 1) * frefstride));
- T12 = _mm_loadu_si128((__m128i*)(fref1 + (i + 2) * frefstride));
- T13 = _mm_loadu_si128((__m128i*)(fref1 + (i + 3) * frefstride));
-
- T14 = _mm_loadu_si128((__m128i*)(fref1 + (i) * frefstride + 16));
- T15 = _mm_loadu_si128((__m128i*)(fref1 + (i + 1) * frefstride + 16));
- T16 = _mm_loadu_si128((__m128i*)(fref1 + (i + 2) * frefstride + 16));
- T17 = _mm_loadu_si128((__m128i*)(fref1 + (i + 3) * frefstride + 16));
-
- T20 = _mm_sad_epu8(T00, T10);
- T21 = _mm_sad_epu8(T01, T11);
- T22 = _mm_sad_epu8(T02, T12);
- T23 = _mm_sad_epu8(T03, T13);
-
- T24 = _mm_sad_epu8(T04, T14);
- T25 = _mm_sad_epu8(T05, T15);
- T26 = _mm_sad_epu8(T06, T16);
- T27 = _mm_sad_epu8(T07, T17);
-
- T20 = _mm_add_epi16(T20, T21);
- T22 = _mm_add_epi16(T22, T23);
-
- T24 = _mm_add_epi16(T24, T25);
- T26 = _mm_add_epi16(T26, T27);
-
- sum0 = _mm_add_epi16(T20, T22);
- sum0 = _mm_add_epi16(sum0, T24);
- sum0 = _mm_add_epi16(sum0, T26);
-
- sum1 = _mm_shuffle_epi32(sum0, 2);
- sum0 = _mm_add_epi32(sum0, sum1);
- res[0] += _mm_cvtsi128_si32(sum0);
-
- T10 = _mm_loadu_si128((__m128i*)(fref2 + (i) * frefstride));
- T11 = _mm_loadu_si128((__m128i*)(fref2 + (i + 1) * frefstride));
- T12 = _mm_loadu_si128((__m128i*)(fref2 + (i + 2) * frefstride));
- T13 = _mm_loadu_si128((__m128i*)(fref2 + (i + 3) * frefstride));
-
- T14 = _mm_loadu_si128((__m128i*)(fref2 + (i) * frefstride + 16));
- T15 = _mm_loadu_si128((__m128i*)(fref2 + (i + 1) * frefstride + 16));
- T16 = _mm_loadu_si128((__m128i*)(fref2 + (i + 2) * frefstride + 16));
- T17 = _mm_loadu_si128((__m128i*)(fref2 + (i + 3) * frefstride + 16));
-
- T20 = _mm_sad_epu8(T00, T10);
- T21 = _mm_sad_epu8(T01, T11);
- T22 = _mm_sad_epu8(T02, T12);
- T23 = _mm_sad_epu8(T03, T13);
-
- T24 = _mm_sad_epu8(T04, T14);
- T25 = _mm_sad_epu8(T05, T15);
- T26 = _mm_sad_epu8(T06, T16);
- T27 = _mm_sad_epu8(T07, T17);
-
- T20 = _mm_add_epi16(T20, T21);
- T22 = _mm_add_epi16(T22, T23);
-
- T24 = _mm_add_epi16(T24, T25);
- T26 = _mm_add_epi16(T26, T27);
-
- sum0 = _mm_add_epi16(T20, T22);
- sum0 = _mm_add_epi16(sum0, T24);
- sum0 = _mm_add_epi16(sum0, T26);
-
- sum1 = _mm_shuffle_epi32(sum0, 2);
- sum0 = _mm_add_epi32(sum0, sum1);
- res[1] += _mm_cvtsi128_si32(sum0);
-
- T10 = _mm_loadu_si128((__m128i*)(fref3 + (i) * frefstride));
- T11 = _mm_loadu_si128((__m128i*)(fref3 + (i + 1) * frefstride));
- T12 = _mm_loadu_si128((__m128i*)(fref3 + (i + 2) * frefstride));
- T13 = _mm_loadu_si128((__m128i*)(fref3 + (i + 3) * frefstride));
-
- T14 = _mm_loadu_si128((__m128i*)(fref3 + (i) * frefstride + 16));
- T15 = _mm_loadu_si128((__m128i*)(fref3 + (i + 1) * frefstride + 16));
- T16 = _mm_loadu_si128((__m128i*)(fref3 + (i + 2) * frefstride + 16));
- T17 = _mm_loadu_si128((__m128i*)(fref3 + (i + 3) * frefstride + 16));
-
- T20 = _mm_sad_epu8(T00, T10);
- T21 = _mm_sad_epu8(T01, T11);
- T22 = _mm_sad_epu8(T02, T12);
- T23 = _mm_sad_epu8(T03, T13);
-
- T24 = _mm_sad_epu8(T04, T14);
- T25 = _mm_sad_epu8(T05, T15);
- T26 = _mm_sad_epu8(T06, T16);
- T27 = _mm_sad_epu8(T07, T17);
-
- T20 = _mm_add_epi16(T20, T21);
- T22 = _mm_add_epi16(T22, T23);
-
- T24 = _mm_add_epi16(T24, T25);
- T26 = _mm_add_epi16(T26, T27);
-
- sum0 = _mm_add_epi16(T20, T22);
- sum0 = _mm_add_epi16(sum0, T24);
- sum0 = _mm_add_epi16(sum0, T26);
-
- sum1 = _mm_shuffle_epi32(sum0, 2);
- sum0 = _mm_add_epi32(sum0, sum1);
- res[2] += _mm_cvtsi128_si32(sum0);
-
- T00 = _mm_load_si128((__m128i*)(fenc + (i + 4) * FENC_STRIDE));
- T01 = _mm_load_si128((__m128i*)(fenc + (i + 5) * FENC_STRIDE));
- T02 = _mm_load_si128((__m128i*)(fenc + (i + 6) * FENC_STRIDE));
- T03 = _mm_load_si128((__m128i*)(fenc + (i + 7) * FENC_STRIDE));
-
- T04 = _mm_load_si128((__m128i*)(fenc + (i + 4) * FENC_STRIDE + 16));
- T05 = _mm_load_si128((__m128i*)(fenc + (i + 5) * FENC_STRIDE + 16));
- T06 = _mm_load_si128((__m128i*)(fenc + (i + 6) * FENC_STRIDE + 16));
- T07 = _mm_load_si128((__m128i*)(fenc + (i + 7) * FENC_STRIDE + 16));
-
- T10 = _mm_loadu_si128((__m128i*)(fref1 + (i + 4) * frefstride));
- T11 = _mm_loadu_si128((__m128i*)(fref1 + (i + 5) * frefstride));
- T12 = _mm_loadu_si128((__m128i*)(fref1 + (i + 6) * frefstride));
- T13 = _mm_loadu_si128((__m128i*)(fref1 + (i + 7) * frefstride));
-
- T14 = _mm_loadu_si128((__m128i*)(fref1 + (i + 4) * frefstride + 16));
- T15 = _mm_loadu_si128((__m128i*)(fref1 + (i + 5) * frefstride + 16));
- T16 = _mm_loadu_si128((__m128i*)(fref1 + (i + 6) * frefstride + 16));
- T17 = _mm_loadu_si128((__m128i*)(fref1 + (i + 7) * frefstride + 16));
-
- T20 = _mm_sad_epu8(T00, T10);
- T21 = _mm_sad_epu8(T01, T11);
- T22 = _mm_sad_epu8(T02, T12);
- T23 = _mm_sad_epu8(T03, T13);
-
- T24 = _mm_sad_epu8(T04, T14);
- T25 = _mm_sad_epu8(T05, T15);
- T26 = _mm_sad_epu8(T06, T16);
- T27 = _mm_sad_epu8(T07, T17);
-
- T20 = _mm_add_epi16(T20, T21);
- T22 = _mm_add_epi16(T22, T23);
-
- T24 = _mm_add_epi16(T24, T25);
- T26 = _mm_add_epi16(T26, T27);
-
- sum0 = _mm_add_epi16(T20, T22);
- sum0 = _mm_add_epi16(sum0, T24);
- sum0 = _mm_add_epi16(sum0, T26);
-
- sum1 = _mm_shuffle_epi32(sum0, 2);
- sum0 = _mm_add_epi32(sum0, sum1);
- res[0] += _mm_cvtsi128_si32(sum0);
-
- T10 = _mm_loadu_si128((__m128i*)(fref2 + (i + 4) * frefstride));
- T11 = _mm_loadu_si128((__m128i*)(fref2 + (i + 5) * frefstride));
- T12 = _mm_loadu_si128((__m128i*)(fref2 + (i + 6) * frefstride));
- T13 = _mm_loadu_si128((__m128i*)(fref2 + (i + 7) * frefstride));
-
- T14 = _mm_loadu_si128((__m128i*)(fref2 + (i + 4) * frefstride + 16));
- T15 = _mm_loadu_si128((__m128i*)(fref2 + (i + 5) * frefstride + 16));
- T16 = _mm_loadu_si128((__m128i*)(fref2 + (i + 6) * frefstride + 16));
- T17 = _mm_loadu_si128((__m128i*)(fref2 + (i + 7) * frefstride + 16));
-
- T20 = _mm_sad_epu8(T00, T10);
- T21 = _mm_sad_epu8(T01, T11);
- T22 = _mm_sad_epu8(T02, T12);
- T23 = _mm_sad_epu8(T03, T13);
-
- T24 = _mm_sad_epu8(T04, T14);
- T25 = _mm_sad_epu8(T05, T15);
- T26 = _mm_sad_epu8(T06, T16);
- T27 = _mm_sad_epu8(T07, T17);
-
- T20 = _mm_add_epi16(T20, T21);
- T22 = _mm_add_epi16(T22, T23);
-
- T24 = _mm_add_epi16(T24, T25);
- T26 = _mm_add_epi16(T26, T27);
-
- sum0 = _mm_add_epi16(T20, T22);
- sum0 = _mm_add_epi16(sum0, T24);
- sum0 = _mm_add_epi16(sum0, T26);
-
- sum1 = _mm_shuffle_epi32(sum0, 2);
- sum0 = _mm_add_epi32(sum0, sum1);
- res[1] += _mm_cvtsi128_si32(sum0);
-
- T10 = _mm_loadu_si128((__m128i*)(fref3 + (i + 4) * frefstride));
- T11 = _mm_loadu_si128((__m128i*)(fref3 + (i + 5) * frefstride));
- T12 = _mm_loadu_si128((__m128i*)(fref3 + (i + 6) * frefstride));
- T13 = _mm_loadu_si128((__m128i*)(fref3 + (i + 7) * frefstride));
-
- T14 = _mm_loadu_si128((__m128i*)(fref3 + (i + 4) * frefstride + 16));
- T15 = _mm_loadu_si128((__m128i*)(fref3 + (i + 5) * frefstride + 16));
- T16 = _mm_loadu_si128((__m128i*)(fref3 + (i + 6) * frefstride + 16));
- T17 = _mm_loadu_si128((__m128i*)(fref3 + (i + 7) * frefstride + 16));
-
- T20 = _mm_sad_epu8(T00, T10);
- T21 = _mm_sad_epu8(T01, T11);
- T22 = _mm_sad_epu8(T02, T12);
- T23 = _mm_sad_epu8(T03, T13);
-
- T24 = _mm_sad_epu8(T04, T14);
- T25 = _mm_sad_epu8(T05, T15);
- T26 = _mm_sad_epu8(T06, T16);
- T27 = _mm_sad_epu8(T07, T17);
-
- T20 = _mm_add_epi16(T20, T21);
- T22 = _mm_add_epi16(T22, T23);
-
- T24 = _mm_add_epi16(T24, T25);
- T26 = _mm_add_epi16(T26, T27);
-
- sum0 = _mm_add_epi16(T20, T22);
- sum0 = _mm_add_epi16(sum0, T24);
- sum0 = _mm_add_epi16(sum0, T26);
-
- sum1 = _mm_shuffle_epi32(sum0, 2);
- sum0 = _mm_add_epi32(sum0, sum1);
- res[2] += _mm_cvtsi128_si32(sum0);
+ PROCESS_32x4x3(i);
+ PROCESS_32x4x3(i + 4);
}
}
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