[x265] [PATCH] filterHorizontal_p_p_4, 12x12 asm code
praveen at multicorewareinc.com
praveen at multicorewareinc.com
Tue Oct 8 08:38:24 CEST 2013
# HG changeset patch
# User Praveen Tiwari
# Date 1381214267 -19800
# Node ID f125c275c2758b8b07ef5ad54274407b46bbdc59
# Parent 5d8d2f4ae188022372fe0282c5eef4c8336e7d37
filterHorizontal_p_p_4, 12x12 asm code
diff -r 5d8d2f4ae188 -r f125c275c275 source/common/x86/ipfilter8.asm
--- a/source/common/x86/ipfilter8.asm Tue Oct 08 11:23:28 2013 +0530
+++ b/source/common/x86/ipfilter8.asm Tue Oct 08 12:07:47 2013 +0530
@@ -241,3 +241,69 @@
FILTER_H4_w8 x0, x1, x2
movh [dstq], x1
RET
+
+ SECTION_RODATA 32
+tab_Tm: db 0, 1, 2, 3, 1, 2, 3, 4, 2, 3, 4, 5, 3, 4, 5, 6
+ db 4, 5, 6, 7, 5, 6, 7, 8, 6, 7, 8, 9, 7, 8, 9, 10
+
+tab_And: dd 0xffffffff, 0xffffffff, 0xffffffff, 0x0
+
+
+tab_c_512: times 8 dw 512
+
+SECTION .text
+
+%macro FILTER_H4_w12 3
+ movu %1, [srcq - 1]
+ pshufb %2, %1, Tm0
+ pmaddubsw %2, coef2
+ pshufb %1, %1, Tm1
+ pmaddubsw %1, coef2
+ phaddw %2, %1
+ pmulhrsw %2, %3
+ movu %1, [srcq - 1 + 8]
+ pshufb %1, %1, Tm0
+ pmaddubsw %1, coef2
+ phaddw %1, %1
+ pmulhrsw %1, %3
+ packuswb %2, %1
+ pand %2, [tab_And]
+%endmacro
+
+%macro FILTER_H4_w12_CALL 0
+ FILTER_H4_w12 x0, x1, x2
+ movu [dstq], x1
+
+ add srcq, srcstrideq
+ add dstq, dststrideq
+%endmacro
+
+;-----------------------------------------------------------------------------
+; void filterHorizontal_p_p_4(pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int width, int height, short const *coeff)
+;-----------------------------------------------------------------------------
+INIT_XMM sse4
+cglobal filterHorizontal_p_p_4, 4, 5, 6, src, srcstride, dst, dststride
+%define coef2 m5
+%define Tm0 m4
+%define Tm1 m3
+%define x2 m2
+%define x1 m1
+%define x0 m0
+
+ mov r4, r6m
+ movu coef2, [r4]
+ packsswb coef2, coef2
+ pshufd coef2, coef2, 0
+
+ mova x2, [tab_c_512]
+
+ mova Tm0, [tab_Tm]
+ mova Tm1, [tab_Tm + 16]
+
+ %rep 11
+ FILTER_H4_w12_CALL
+ %endrep
+
+ FILTER_H4_w12 x0, x1, x2
+ movu [dstq], x1
+ RET
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