[x265] [PATCH UPDATE] asm: cvt32to16_shr_sse2

[Min Chen]

# HG changeset patch
# User Min Chen <chenm003 at 163.com>
# Date 1382025002 -28800
# Node ID ecd0378bf284026478454495b32afed1fddffd26
# Parent  03370e851f3b754d4a8531e8ade92fca43de5cc4
asm: cvt32to16_shr_sse2

diff -r 03370e851f3b -r ecd0378bf284 source/common/CMakeLists.txt
--- a/source/common/CMakeLists.txt	Thu Oct 17 23:49:38 2013 +0800
+++ b/source/common/CMakeLists.txt	Thu Oct 17 23:50:02 2013 +0800
@@ -153,7 +153,7 @@
         add_definitions(-DHAVE_ALIGNED_STACK=0)
     endif()
 
-    set(ASMS pixel-a.asm const-a.asm cpu-a.asm sad-a.asm mc-a.asm mc-a2.asm ipfilter8.asm)
+    set(ASMS pixel-a.asm const-a.asm cpu-a.asm sad-a.asm mc-a.asm mc-a2.asm ipfilter8.asm pixel-util.asm)
     if (X64)
         add_definitions(-DARCH_X86_64=1)
     else()
diff -r 03370e851f3b -r ecd0378bf284 source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp	Thu Oct 17 23:49:38 2013 +0800
+++ b/source/common/x86/asm-primitives.cpp	Thu Oct 17 23:50:02 2013 +0800
@@ -312,6 +312,8 @@
         p.sa8d[BLOCK_8x8]   = x265_pixel_sa8d_8x8_sse2;
         p.sa8d[BLOCK_16x16] = x265_pixel_sa8d_16x16_sse2;
         SA8D_INTER_FROM_BLOCK(sse2);
+
+        p.cvt32to16_shr = x265_cvt32to16_shr_sse2;
     }
     if (cpuMask & X265_CPU_SSSE3)
     {
diff -r 03370e851f3b -r ecd0378bf284 source/common/x86/pixel.h
--- a/source/common/x86/pixel.h	Thu Oct 17 23:49:38 2013 +0800
+++ b/source/common/x86/pixel.h	Thu Oct 17 23:50:02 2013 +0800
@@ -201,6 +201,8 @@
 uint64_t x265_pixel_sa8d_satd_16x16_xop(pixel *pix1, intptr_t stride1, pixel *pix2, intptr_t stride2);
 uint64_t x265_pixel_sa8d_satd_16x16_avx2(pixel *pix1, intptr_t stride1, pixel *pix2, intptr_t stride2);
 
+void x265_cvt32to16_shr_sse2(short *dst, int *src, intptr_t, int, int);
+
 #define DECL_SSD(width, suffix) \
     int x265_pixel_ssd_ ## width ## x64_ ## suffix(pixel *, intptr_t, pixel *, intptr_t); \
     int x265_pixel_ssd_ ## width ## x48_ ## suffix(pixel *, intptr_t, pixel *, intptr_t); \