[x265] [PATCH Review Only] asm code for interp_4tap_vert_pp_2x4
praveen at multicorewareinc.com
praveen at multicorewareinc.com
Mon Oct 28 13:03:07 CET 2013
# HG changeset patch
# User Praveen Tiwari
# Date 1382961770 -19800
# Node ID d62d12b69145ffdfb5d645ebe1f452c294fa5876
# Parent 14ae0b70567b0d78738f2cb064b25c46e437d950
asm code for interp_4tap_vert_pp_2x4
diff -r 14ae0b70567b -r d62d12b69145 source/common/x86/ipfilter8.asm
--- a/source/common/x86/ipfilter8.asm Mon Oct 28 16:47:51 2013 +0530
+++ b/source/common/x86/ipfilter8.asm Mon Oct 28 17:32:50 2013 +0530
@@ -38,6 +38,8 @@
tab_Vm: db 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1
db 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3
+tab_Cm: db 0, 2, 1, 3, 0, 2, 1, 3, 0, 2, 1, 3, 0, 2, 1, 3
+
tab_c_512: times 8 dw 512
tab_ChromaCoeff: db 0, 64, 0, 0
@@ -723,3 +725,79 @@
%endmacro
FILTER_V4_W12_H2 12, 16
+
+;-----------------------------------------------------------------------------
+;void interp_4tap_vert_pp_2x4(pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx)
+;-----------------------------------------------------------------------------
+INIT_XMM sse4
+cglobal interp_4tap_vert_pp_2x4, 4, 7, 8
+
+mov r4d, r4m
+sub r0, r1
+
+%ifdef PIC
+lea r5, [tab_ChromaCoeff]
+movd m0, [r5 + r4 * 4]
+%else
+movd m0, [tab_ChromaCoeff + r4 * 4]
+%endif
+
+pshufb m0, [tab_Cm]
+
+mova m1, [tab_c_512]
+
+movd m2, [r0]
+movd m3, [r0 + r1]
+movd m4, [r0 + 2 * r1]
+lea r5, [r0 + 2 * r1]
+movd m5, [r5 + r1]
+
+punpcklbw m2, m3
+punpcklbw m6, m4, m5
+punpcklbw m2, m6
+
+pmaddubsw m2, m0
+
+movd m6, [r0 + 4 * r1]
+
+punpcklbw m3, m4
+punpcklbw m7, m5, m6
+punpcklbw m3, m7
+
+pmaddubsw m3, m0
+
+phaddw m2, m3
+
+pmulhrsw m2, m1
+packuswb m2, m2
+
+pextrw [r2], m2, 0
+pextrw [r2 + r3], m2, 2
+
+lea r5, [r0 + 4 * r1]
+movd m2, [r5 + r1]
+
+punpcklbw m4, m5
+punpcklbw m3, m6, m2
+punpcklbw m4, m3
+
+pmaddubsw m4, m0
+
+movd m3, [r5 + 2 * r1]
+
+punpcklbw m5, m6
+punpcklbw m2, m3
+punpcklbw m5, m2
+
+pmaddubsw m5, m0
+
+phaddw m4, m5
+
+pmulhrsw m4, m1
+packuswb m4, m4
+
+pextrw [r2 + 2 * r3], m4, 0
+lea r6, [r2 + 2 * r3]
+pextrw [r6 + r3], m4, 2
+
+RET
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