[x265] [PATCH] pixel: remove sad_16, sad_x3_16 and sad_x4_16
Steve Borho
steve at borho.org
Tue Oct 29 21:43:41 CET 2013
# HG changeset patch
# User Steve Borho <steve at borho.org>
# Date 1383079398 18000
# Tue Oct 29 15:43:18 2013 -0500
# Node ID 42ae4dc9000558c0d3862cf4f9e5952b6a6fbcd7
# Parent c946d617fd9fbd2ae237d5ba7d8338a1a3f5ea7d
pixel: remove sad_16, sad_x3_16 and sad_x4_16
We have assembly coverage for everything but sad_16x12; which I've put on the
top of our TODO list.
diff -r c946d617fd9f -r 42ae4dc90005 source/common/vec/pixel-sse41.cpp
--- a/source/common/vec/pixel-sse41.cpp Tue Oct 29 15:16:28 2013 +0530
+++ b/source/common/vec/pixel-sse41.cpp Tue Oct 29 15:43:18 2013 -0500
@@ -256,61 +256,6 @@
}
template<int ly>
-int sad_16(pixel * fenc, intptr_t fencstride, pixel * fref, intptr_t frefstride)
-{
- __m128i sum0 = _mm_setzero_si128();
- __m128i sum1 = _mm_setzero_si128();
- __m128i T00, T01, T02, T03;
- __m128i T10, T11, T12, T13;
- __m128i T20, T21, T22, T23;
-
-#define PROCESS_16x4(BASE) \
- T00 = _mm_load_si128((__m128i*)(fenc + (BASE + 0) * fencstride)); \
- T01 = _mm_load_si128((__m128i*)(fenc + (BASE + 1) * fencstride)); \
- T02 = _mm_load_si128((__m128i*)(fenc + (BASE + 2) * fencstride)); \
- T03 = _mm_load_si128((__m128i*)(fenc + (BASE + 3) * fencstride)); \
- T10 = _mm_loadu_si128((__m128i*)(fref + (BASE + 0) * frefstride)); \
- T11 = _mm_loadu_si128((__m128i*)(fref + (BASE + 1) * frefstride)); \
- T12 = _mm_loadu_si128((__m128i*)(fref + (BASE + 2) * frefstride)); \
- T13 = _mm_loadu_si128((__m128i*)(fref + (BASE + 3) * frefstride)); \
- T20 = _mm_sad_epu8(T00, T10); \
- T21 = _mm_sad_epu8(T01, T11); \
- T22 = _mm_sad_epu8(T02, T12); \
- T23 = _mm_sad_epu8(T03, T13); \
- sum0 = _mm_add_epi16(sum0, T20); \
- sum0 = _mm_add_epi16(sum0, T21); \
- sum0 = _mm_add_epi16(sum0, T22); \
- sum0 = _mm_add_epi16(sum0, T23)
-
- PROCESS_16x4(0);
- if (ly >= 8)
- {
- PROCESS_16x4(4);
- }
- if (ly >= 12)
- {
- PROCESS_16x4(8);
- }
- if (ly >= 16)
- {
- PROCESS_16x4(12);
- }
- if (ly > 16)
- {
- for (int i = 16; i < ly; i += 8)
- {
- PROCESS_16x4(i);
- PROCESS_16x4(i + 4);
- }
- }
-
- sum1 = _mm_shuffle_epi32(sum0, 2);
- sum0 = _mm_add_epi32(sum0, sum1);
-
- return _mm_cvtsi128_si32(sum0);
-}
-
-template<int ly>
// always instanced for 32 rows
int sad_24(pixel *fenc, intptr_t fencstride, pixel *fref, intptr_t frefstride)
{
@@ -1445,89 +1390,6 @@
}
template<int ly>
-void sad_x3_16(pixel *fenc, pixel *fref1, pixel *fref2, pixel *fref3, intptr_t frefstride, int32_t *res)
-{
-#define PROCESS_16x4x3(BASE) \
- T00 = _mm_load_si128((__m128i*)(fenc + (BASE + 0) * FENC_STRIDE)); \
- T01 = _mm_load_si128((__m128i*)(fenc + (BASE + 1) * FENC_STRIDE)); \
- T02 = _mm_load_si128((__m128i*)(fenc + (BASE + 2) * FENC_STRIDE)); \
- T03 = _mm_load_si128((__m128i*)(fenc + (BASE + 3) * FENC_STRIDE)); \
- T10 = _mm_loadu_si128((__m128i*)(fref1 + (BASE + 0) * frefstride)); \
- T11 = _mm_loadu_si128((__m128i*)(fref1 + (BASE + 1) * frefstride)); \
- T12 = _mm_loadu_si128((__m128i*)(fref1 + (BASE + 2) * frefstride)); \
- T13 = _mm_loadu_si128((__m128i*)(fref1 + (BASE + 3) * frefstride)); \
- T20 = _mm_sad_epu8(T00, T10); \
- T21 = _mm_sad_epu8(T01, T11); \
- T22 = _mm_sad_epu8(T02, T12); \
- T23 = _mm_sad_epu8(T03, T13); \
- T20 = _mm_add_epi16(T20, T21); \
- T22 = _mm_add_epi16(T22, T23); \
- sum0 = _mm_add_epi16(T20, T22); \
- sum1 = _mm_shuffle_epi32(sum0, 2); \
- sum0 = _mm_add_epi32(sum0, sum1); \
- res0 += _mm_cvtsi128_si32(sum0); \
- T10 = _mm_loadu_si128((__m128i*)(fref2 + (BASE + 0) * frefstride)); \
- T11 = _mm_loadu_si128((__m128i*)(fref2 + (BASE + 1) * frefstride)); \
- T12 = _mm_loadu_si128((__m128i*)(fref2 + (BASE + 2) * frefstride)); \
- T13 = _mm_loadu_si128((__m128i*)(fref2 + (BASE + 3) * frefstride)); \
- T20 = _mm_sad_epu8(T00, T10); \
- T21 = _mm_sad_epu8(T01, T11); \
- T22 = _mm_sad_epu8(T02, T12); \
- T23 = _mm_sad_epu8(T03, T13); \
- T20 = _mm_add_epi16(T20, T21); \
- T22 = _mm_add_epi16(T22, T23); \
- sum0 = _mm_add_epi16(T20, T22); \
- sum1 = _mm_shuffle_epi32(sum0, 2); \
- sum0 = _mm_add_epi32(sum0, sum1); \
- res1 += _mm_cvtsi128_si32(sum0); \
- T10 = _mm_loadu_si128((__m128i*)(fref3 + (BASE + 0) * frefstride)); \
- T11 = _mm_loadu_si128((__m128i*)(fref3 + (BASE + 1) * frefstride)); \
- T12 = _mm_loadu_si128((__m128i*)(fref3 + (BASE + 2) * frefstride)); \
- T13 = _mm_loadu_si128((__m128i*)(fref3 + (BASE + 3) * frefstride)); \
- T20 = _mm_sad_epu8(T00, T10); \
- T21 = _mm_sad_epu8(T01, T11); \
- T22 = _mm_sad_epu8(T02, T12); \
- T23 = _mm_sad_epu8(T03, T13); \
- T20 = _mm_add_epi16(T20, T21); \
- T22 = _mm_add_epi16(T22, T23); \
- sum0 = _mm_add_epi16(T20, T22); \
- sum1 = _mm_shuffle_epi32(sum0, 2); \
- sum0 = _mm_add_epi32(sum0, sum1); \
- res2 += _mm_cvtsi128_si32(sum0); \
-
- __m128i T00, T01, T02, T03;
- __m128i T10, T11, T12, T13;
- __m128i T20, T21, T22, T23;
- __m128i sum0, sum1;
- int res0 = 0, res1 = 0, res2 = 0;
-
- // ly == 4, 12, 32, 64
- PROCESS_16x4x3(0);
- if (ly >= 8)
- {
- PROCESS_16x4x3(4);
- }
- if (ly >= 12)
- {
- PROCESS_16x4x3(8);
- }
- if (ly > 12)
- {
- PROCESS_16x4x3(12);
- for (int i = 16; i < ly; i += 16)
- {
- PROCESS_16x4x3(i);
- PROCESS_16x4x3(i + 4);
- PROCESS_16x4x3(i + 8);
- PROCESS_16x4x3(i + 12);
- }
- }
- res[0] = res0;
- res[1] = res1;
- res[2] = res2;
-}
-
-template<int ly>
void sad_x3_24(pixel *fenc, pixel *fref1, pixel *fref2, pixel *fref3, intptr_t frefstride, int32_t *res)
{
res[0] = res[1] = res[2] = 0;
@@ -3357,104 +3219,6 @@
}
template<int ly>
-void sad_x4_16(pixel *fenc, pixel *fref1, pixel *fref2, pixel *fref3, pixel *fref4, intptr_t frefstride, int32_t *res)
-{
-#define PROCESS_16x4x4(BASE) \
- T00 = _mm_load_si128((__m128i*)(fenc + (BASE + 0) * FENC_STRIDE)); \
- T01 = _mm_load_si128((__m128i*)(fenc + (BASE + 1) * FENC_STRIDE)); \
- T02 = _mm_load_si128((__m128i*)(fenc + (BASE + 2) * FENC_STRIDE)); \
- T03 = _mm_load_si128((__m128i*)(fenc + (BASE + 3) * FENC_STRIDE)); \
- T10 = _mm_loadu_si128((__m128i*)(fref1 + (BASE + 0) * frefstride)); \
- T11 = _mm_loadu_si128((__m128i*)(fref1 + (BASE + 1) * frefstride)); \
- T12 = _mm_loadu_si128((__m128i*)(fref1 + (BASE + 2) * frefstride)); \
- T13 = _mm_loadu_si128((__m128i*)(fref1 + (BASE + 3) * frefstride)); \
- T20 = _mm_sad_epu8(T00, T10); \
- T21 = _mm_sad_epu8(T01, T11); \
- T22 = _mm_sad_epu8(T02, T12); \
- T23 = _mm_sad_epu8(T03, T13); \
- T20 = _mm_add_epi16(T20, T21); \
- T22 = _mm_add_epi16(T22, T23); \
- sum0 = _mm_add_epi16(T20, T22); \
- sum1 = _mm_shuffle_epi32(sum0, 2); \
- sum0 = _mm_add_epi32(sum0, sum1); \
- res0 += _mm_cvtsi128_si32(sum0); \
- T10 = _mm_loadu_si128((__m128i*)(fref2 + (BASE + 0) * frefstride)); \
- T11 = _mm_loadu_si128((__m128i*)(fref2 + (BASE + 1) * frefstride)); \
- T12 = _mm_loadu_si128((__m128i*)(fref2 + (BASE + 2) * frefstride)); \
- T13 = _mm_loadu_si128((__m128i*)(fref2 + (BASE + 3) * frefstride)); \
- T20 = _mm_sad_epu8(T00, T10); \
- T21 = _mm_sad_epu8(T01, T11); \
- T22 = _mm_sad_epu8(T02, T12); \
- T23 = _mm_sad_epu8(T03, T13); \
- T20 = _mm_add_epi16(T20, T21); \
- T22 = _mm_add_epi16(T22, T23); \
- sum0 = _mm_add_epi16(T20, T22); \
- sum1 = _mm_shuffle_epi32(sum0, 2); \
- sum0 = _mm_add_epi32(sum0, sum1); \
- res1 += _mm_cvtsi128_si32(sum0); \
- T10 = _mm_loadu_si128((__m128i*)(fref3 + (BASE + 0) * frefstride)); \
- T11 = _mm_loadu_si128((__m128i*)(fref3 + (BASE + 1) * frefstride)); \
- T12 = _mm_loadu_si128((__m128i*)(fref3 + (BASE + 2) * frefstride)); \
- T13 = _mm_loadu_si128((__m128i*)(fref3 + (BASE + 3) * frefstride)); \
- T20 = _mm_sad_epu8(T00, T10); \
- T21 = _mm_sad_epu8(T01, T11); \
- T22 = _mm_sad_epu8(T02, T12); \
- T23 = _mm_sad_epu8(T03, T13); \
- T20 = _mm_add_epi16(T20, T21); \
- T22 = _mm_add_epi16(T22, T23); \
- sum0 = _mm_add_epi16(T20, T22); \
- sum1 = _mm_shuffle_epi32(sum0, 2); \
- sum0 = _mm_add_epi32(sum0, sum1); \
- res2 += _mm_cvtsi128_si32(sum0); \
- T10 = _mm_loadu_si128((__m128i*)(fref4 + (BASE + 0) * frefstride)); \
- T11 = _mm_loadu_si128((__m128i*)(fref4 + (BASE + 1) * frefstride)); \
- T12 = _mm_loadu_si128((__m128i*)(fref4 + (BASE + 2) * frefstride)); \
- T13 = _mm_loadu_si128((__m128i*)(fref4 + (BASE + 3) * frefstride)); \
- T20 = _mm_sad_epu8(T00, T10); \
- T21 = _mm_sad_epu8(T01, T11); \
- T22 = _mm_sad_epu8(T02, T12); \
- T23 = _mm_sad_epu8(T03, T13); \
- T20 = _mm_add_epi16(T20, T21); \
- T22 = _mm_add_epi16(T22, T23); \
- sum0 = _mm_add_epi16(T20, T22); \
- sum1 = _mm_shuffle_epi32(sum0, 2); \
- sum0 = _mm_add_epi32(sum0, sum1); \
- res3 += _mm_cvtsi128_si32(sum0); \
-
- __m128i T00, T01, T02, T03;
- __m128i T10, T11, T12, T13;
- __m128i T20, T21, T22, T23;
- __m128i sum0, sum1;
- int res0 = 0, res1 = 0, res2 = 0, res3 = 0;
-
- // ly == 4, 12, 32, 64
- PROCESS_16x4x4(0);
- if (ly >= 8)
- {
- PROCESS_16x4x4(4);
- }
- if (ly >= 12)
- {
- PROCESS_16x4x4(8);
- }
- if (ly > 12)
- {
- PROCESS_16x4x4(12);
- for (int i = 16; i < ly; i += 16)
- {
- PROCESS_16x4x4(i);
- PROCESS_16x4x4(i + 4);
- PROCESS_16x4x4(i + 8);
- PROCESS_16x4x4(i + 12);
- }
- }
- res[0] = res0;
- res[1] = res1;
- res[2] = res2;
- res[3] = res3;
-}
-
-template<int ly>
void sad_x4_24(pixel *fenc, pixel *fref1, pixel *fref2, pixel *fref3, pixel *fref4, intptr_t frefstride, int32_t *res)
{
res[0] = res[1] = res[2] = res[3] = 0;
@@ -5619,12 +5383,12 @@
SETUP_PARTITION(32, 64);
SETUP_PARTITION(64, 16);
SETUP_PARTITION(64, 48);
- SETUP_PARTITION(16, 64);
+ SETUP_NONSAD(16, 64);
SETUP_PARTITION(48, 64);
SETUP_PARTITION(32, 32);
SETUP_PARTITION(32, 16);
- SETUP_PARTITION(16, 32);
+ SETUP_NONSAD(16, 32);
SETUP_PARTITION(32, 8);
SETUP_PARTITION(32, 24);
SETUP_PARTITION(8, 32);
@@ -5633,8 +5397,8 @@
SETUP_NONSAD(16, 16); // 16x16 SAD covered by assembly
SETUP_NONSAD(16, 8); // 16x8 SAD covered by assembly
SETUP_NONSAD(8, 16); // 8x16 SAD covered by assembly
- SETUP_PARTITION(16, 4);
- SETUP_PARTITION(16, 12);
+ SETUP_NONSAD(16, 4);
+ SETUP_NONSAD(16, 12);
SETUP_NONSAD(4, 16); // 4x16 SAD covered by assembly
#if !defined(__clang__)
SETUP_PARTITION(12, 16);
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