[x265] [PATCH] assembly code for pixel_sad_x4_32xN

yuvaraj at multicorewareinc.com yuvaraj at multicorewareinc.com
Wed Oct 30 14:28:41 CET 2013


# HG changeset patch
# User Yuvaraj Venkatesh <yuvaraj at multicorewareinc.com>
# Date 1383139673 -19800
#      Wed Oct 30 18:57:53 2013 +0530
# Node ID 5a828f8314c69c2ac6fd2cab963b8c29af83d78c
# Parent  baf2012ba47fa100a3c739ca68a6207fa22eb931
assembly code for pixel_sad_x4_32xN

diff -r baf2012ba47f -r 5a828f8314c6 source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp	Wed Oct 30 18:41:40 2013 +0530
+++ b/source/common/x86/asm-primitives.cpp	Wed Oct 30 18:57:53 2013 +0530
@@ -299,6 +299,11 @@
         p.sad_x3[LUMA_32x24] = x265_pixel_sad_x3_32x24_ssse3;
         p.sad_x3[LUMA_32x32] = x265_pixel_sad_x3_32x32_ssse3;
         p.sad_x3[LUMA_32x64] = x265_pixel_sad_x3_32x64_ssse3;
+        p.sad_x4[LUMA_32x8] = x265_pixel_sad_x4_32x8_ssse3;
+        p.sad_x4[LUMA_32x16] = x265_pixel_sad_x4_32x16_ssse3;
+        p.sad_x4[LUMA_32x24] = x265_pixel_sad_x4_32x24_ssse3;
+        p.sad_x4[LUMA_32x32] = x265_pixel_sad_x4_32x32_ssse3;
+        p.sad_x4[LUMA_32x64] = x265_pixel_sad_x4_32x64_ssse3;
 
         p.luma_hvpp[LUMA_8x8] = x265_interp_8tap_hv_pp_8x8_ssse3;
         p.ipfilter_sp[FILTER_V_S_P_8] = x265_interp_8tap_v_sp_ssse3;
@@ -339,6 +344,11 @@
         p.sad_x3[LUMA_32x24] = x265_pixel_sad_x3_32x24_avx;
         p.sad_x3[LUMA_32x32] = x265_pixel_sad_x3_32x32_avx;
         p.sad_x3[LUMA_32x64] = x265_pixel_sad_x3_32x64_avx;
+        p.sad_x4[LUMA_32x8] = x265_pixel_sad_x4_32x8_avx;
+        p.sad_x4[LUMA_32x16] = x265_pixel_sad_x4_32x16_avx;
+        p.sad_x4[LUMA_32x24] = x265_pixel_sad_x4_32x24_avx;
+        p.sad_x4[LUMA_32x32] = x265_pixel_sad_x4_32x32_avx;
+        p.sad_x4[LUMA_32x64] = x265_pixel_sad_x4_32x64_avx;
     }
     if (cpuMask & X265_CPU_XOP)
     {
diff -r baf2012ba47f -r 5a828f8314c6 source/common/x86/sad-a.asm
--- a/source/common/x86/sad-a.asm	Wed Oct 30 18:41:40 2013 +0530
+++ b/source/common/x86/sad-a.asm	Wed Oct 30 18:57:53 2013 +0530
@@ -2341,6 +2341,133 @@
     lea     r3,  [r3 + r4]
 %endmacro
 
+%macro SAD_X4_32x4 0
+    mova    m4,  [r0]
+    mova    m5,  [r0 + 16]
+    movu    m6,  [r1]
+    movu    m7,  [r1 + 16]
+    psadbw  m6,  m4
+    psadbw  m7,  m5
+    paddd   m6,  m7
+    paddd   m0,  m6
+    movu    m6,  [r2]
+    movu    m7,  [r2 + 16]
+    psadbw  m6,  m4
+    psadbw  m7,  m5
+    paddd   m6,  m7
+    paddd   m1,  m6
+    movu    m6,  [r3]
+    movu    m7,  [r3 + 16]
+    psadbw  m6,  m4
+    psadbw  m7,  m5
+    paddd   m6,  m7
+    paddd   m2,  m6
+    movu    m6,  [r4]
+    movu    m7,  [r4 + 16]
+    psadbw  m6,  m4
+    psadbw  m7,  m5
+    paddd   m6,  m7
+    paddd   m3,  m6
+    lea     r0,  [r0 + FENC_STRIDE]
+    lea     r1,  [r1 + r5]
+    lea     r2,  [r2 + r5]
+    lea     r3,  [r3 + r5]
+    lea     r4,  [r4 + r5]
+    mova    m4,  [r0]
+    mova    m5,  [r0 + 16]
+    movu    m6,  [r1]
+    movu    m7,  [r1 + 16]
+    psadbw  m6,  m4
+    psadbw  m7,  m5
+    paddd   m6,  m7
+    paddd   m0,  m6
+    movu    m6,  [r2]
+    movu    m7,  [r2 + 16]
+    psadbw  m6,  m4
+    psadbw  m7,  m5
+    paddd   m6,  m7
+    paddd   m1,  m6
+    movu    m6,  [r3]
+    movu    m7,  [r3 + 16]
+    psadbw  m6,  m4
+    psadbw  m7,  m5
+    paddd   m6,  m7
+    paddd   m2,  m6
+    movu    m6,  [r4]
+    movu    m7,  [r4 + 16]
+    psadbw  m6,  m4
+    psadbw  m7,  m5
+    paddd   m6,  m7
+    paddd   m3,  m6
+    lea     r0,  [r0 + FENC_STRIDE]
+    lea     r1,  [r1 + r5]
+    lea     r2,  [r2 + r5]
+    lea     r3,  [r3 + r5]
+    lea     r4,  [r4 + r5]
+    mova    m4,  [r0]
+    mova    m5,  [r0 + 16]
+    movu    m6,  [r1]
+    movu    m7,  [r1 + 16]
+    psadbw  m6,  m4
+    psadbw  m7,  m5
+    paddd   m6,  m7
+    paddd   m0,  m6
+    movu    m6,  [r2]
+    movu    m7,  [r2 + 16]
+    psadbw  m6,  m4
+    psadbw  m7,  m5
+    paddd   m6,  m7
+    paddd   m1,  m6
+    movu    m6,  [r3]
+    movu    m7,  [r3 + 16]
+    psadbw  m6,  m4
+    psadbw  m7,  m5
+    paddd   m6,  m7
+    paddd   m2,  m6
+    movu    m6,  [r4]
+    movu    m7,  [r4 + 16]
+    psadbw  m6,  m4
+    psadbw  m7,  m5
+    paddd   m6,  m7
+    paddd   m3,  m6
+    lea     r0,  [r0 + FENC_STRIDE]
+    lea     r1,  [r1 + r5]
+    lea     r2,  [r2 + r5]
+    lea     r3,  [r3 + r5]
+    lea     r4,  [r4 + r5]
+    mova    m4,  [r0]
+    mova    m5,  [r0 + 16]
+    movu    m6,  [r1]
+    movu    m7,  [r1 + 16]
+    psadbw  m6,  m4
+    psadbw  m7,  m5
+    paddd   m6,  m7
+    paddd   m0,  m6
+    movu    m6,  [r2]
+    movu    m7,  [r2 + 16]
+    psadbw  m6,  m4
+    psadbw  m7,  m5
+    paddd   m6,  m7
+    paddd   m1,  m6
+    movu    m6,  [r3]
+    movu    m7,  [r3 + 16]
+    psadbw  m6,  m4
+    psadbw  m7,  m5
+    paddd   m6,  m7
+    paddd   m2,  m6
+    movu    m6,  [r4]
+    movu    m7,  [r4 + 16]
+    psadbw  m6,  m4
+    psadbw  m7,  m5
+    paddd   m6,  m7
+    paddd   m3,  m6
+    lea     r0,  [r0 + FENC_STRIDE]
+    lea     r1,  [r1 + r5]
+    lea     r2,  [r2 + r5]
+    lea     r3,  [r3 + r5]
+    lea     r4,  [r4 + r5]
+%endmacro
+
 ;-----------------------------------------------------------------------------
 ; void pixel_sad_x3_16x16( uint8_t *fenc, uint8_t *pix0, uint8_t *pix1,
 ;                          uint8_t *pix2, intptr_t i_stride, int scores[3] )
@@ -2467,6 +2594,81 @@
     SAD_X3_END_SSE2 1
 %endmacro
 
+%macro SAD_X4_W32 0
+cglobal pixel_sad_x4_32x8, 6, 7, 8
+    pxor  m0, m0
+    pxor  m1, m1
+    pxor  m2, m2
+    pxor  m3, m3
+
+    SAD_X4_32x4
+    SAD_X4_32x4
+    SAD_X4_END_SSE2 1
+
+cglobal pixel_sad_x4_32x16, 6, 7, 8
+    pxor  m0, m0
+    pxor  m1, m1
+    pxor  m2, m2
+    pxor  m3, m3
+
+    SAD_X4_32x4
+    SAD_X4_32x4
+    SAD_X4_32x4
+    SAD_X4_32x4
+    SAD_X4_END_SSE2 1
+
+cglobal pixel_sad_x4_32x24, 6, 7, 8
+    pxor  m0, m0
+    pxor  m1, m1
+    pxor  m2, m2
+    pxor  m3, m3
+
+    SAD_X4_32x4
+    SAD_X4_32x4
+    SAD_X4_32x4
+    SAD_X4_32x4
+    SAD_X4_32x4
+    SAD_X4_32x4
+    SAD_X4_END_SSE2 1
+
+cglobal pixel_sad_x4_32x32, 6, 8, 8
+    pxor  m0, m0
+    pxor  m1, m1
+    pxor  m2, m2
+    pxor  m3, m3
+    mov   r7, 32
+
+.loop
+    SAD_X4_32x4
+    SAD_X4_32x4
+    SAD_X4_32x4
+    SAD_X4_32x4
+
+    sub r7,  16
+    cmp r7,  0
+jnz .loop
+    SAD_X4_END_SSE2 1
+
+cglobal pixel_sad_x4_32x64, 6, 8, 8
+    pxor  m0, m0
+    pxor  m1, m1
+    pxor  m2, m2
+    pxor  m3, m3
+    mov   r7, 64
+
+.loop1
+    SAD_X4_32x4
+    SAD_X4_32x4
+    SAD_X4_32x4
+    SAD_X4_32x4
+
+    sub r7,  16
+    cmp r7,  0
+jnz .loop1
+    SAD_X4_END_SSE2 1
+%endmacro
+
+
 INIT_XMM sse2
 SAD_X_SSE2 3, 16, 16, 7
 SAD_X_SSE2 3, 16,  8, 7
@@ -2508,6 +2710,7 @@
 SAD_X_SSE2  3,  8, 32, 7
 SAD_X_SSE2  3,  8, 16, 7
 SAD_X4_W24
+SAD_X4_W32
 SAD_X_SSE2  4, 16, 64, 7
 SAD_X_SSE2  4, 16, 32, 7
 SAD_X_SSE2  4, 16, 16, 7
@@ -2528,6 +2731,7 @@
 SAD_X_SSE2 3, 16,  8, 6
 SAD_X_SSE2 3, 16,  4, 6
 SAD_X4_W24
+SAD_X4_W32
 SAD_X_SSE2 4, 16, 64, 7
 SAD_X_SSE2 4, 16, 32, 7
 SAD_X_SSE2 4, 16, 16, 7


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