[x265] [PATCH] Fix crash bug on AWS Server (all physics multi CPU system)

[Min Chen]

# HG changeset patch
# User Min Chen <chenm003 at 163.com>
# Date 1391147125 -28800
# Node ID c741b666cace2499765312b6aa7aa4eb9303765f
# Parent  8552e8cc1a3c60ddcab85e7421229c9a86d4785f
Fix crash bug on AWS Server (all physics multi CPU system)

This bug on our ATOMIC_CAS, it mapping to 'LOCK CMPXCHG' instruction.
In Intel instruction manual, it isn't any specially description.

But on MSDN: 'The variables for this function must be aligned on a 64-bit boundary; otherwise, this function will behave unpredictably on multiprocessor x86 systems and any non-x86 systems.'

So we alignment flag buffer to avoid this bug.

diff -r 8552e8cc1a3c -r c741b666cace source/common/wavefront.cpp
--- a/source/common/wavefront.cpp	Tue Jan 28 08:49:01 2014 -0600
+++ b/source/common/wavefront.cpp	Fri Jan 31 13:45:25 2014 +0800
@@ -24,6 +24,7 @@
 #include "threadpool.h"
 #include "threading.h"
 #include "wavefront.h"
+#include "TLibCommon/CommonDef.h"  // X265_MALLOC, X265_FREE
 #include <assert.h>
 #include <string.h>
 #include <new>
@@ -38,11 +39,11 @@
     if (m_pool)
     {
         m_numWords = (numRows + 63) >> 6;
-        m_queuedBitmap = new uint64_t[m_numWords];
+        m_queuedBitmap = (uint64_t *)X265_MALLOC(uint64_t, m_numWords);
         if (m_queuedBitmap)
             memset((void*)m_queuedBitmap, 0, sizeof(uint64_t) * m_numWords);
 
-        m_enableBitmap = new uint64_t[m_numWords];
+        m_enableBitmap = (uint64_t *)X265_MALLOC(uint64_t, m_numWords);
         if (m_enableBitmap)
             memset((void*)m_enableBitmap, 0, sizeof(uint64_t) * m_numWords);
 
@@ -54,8 +55,8 @@
 
 WaveFront::~WaveFront()
 {
-    delete[] m_queuedBitmap;
-    delete[] m_enableBitmap;
+    X265_FREE((void *)m_queuedBitmap);
+    X265_FREE((void *)m_enableBitmap);
 }
 
 void WaveFront::clearEnabledRowMask()
@@ -115,13 +116,14 @@
         while (m_queuedBitmap[w])
         {
             uint64_t oldval = m_queuedBitmap[w];
-            uint64_t mask = m_queuedBitmap[w] & m_enableBitmap[w];
+            uint64_t mask = oldval & m_enableBitmap[w];
             if (mask == 0) // race condition
                 break;
 
             CTZ64(id, mask);
 
             uint64_t newval = oldval & ~(1LL << id);
+            assert(0 == ((int)&m_queuedBitmap[w]) % 8);
             if (ATOMIC_CAS(&m_queuedBitmap[w], oldval, newval) == oldval)
             {
                 // we cleared the bit, process row