[x265] [PATCH 4 of 7] asm: intra_pred_ang4_27 improved by ~35% over SSE4, 146.71c -> 95.03c

[praveen at multicorewareinc.com]

# HG changeset patch
# User Praveen Tiwari <praveen at multicorewareinc.com>
# Date 1427888202 -19800
#      Wed Apr 01 17:06:42 2015 +0530
# Node ID aa58202ff26fd43f930a1b48cd1389af6c8bf31e
# Parent  4750af9d9af47c4d82acb58d5aae12e1c7e7268d
asm: intra_pred_ang4_27 improved by ~35% over SSE4, 146.71c -> 95.03c

diff -r 4750af9d9af4 -r aa58202ff26f source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp	Wed Apr 01 15:43:16 2015 +0530
+++ b/source/common/x86/asm-primitives.cpp	Wed Apr 01 17:06:42 2015 +0530
@@ -1606,6 +1606,7 @@
         p.weight_pp = x265_weight_pp_avx2;
 
         // intra_pred functions
+        p.cu[BLOCK_4x4].intra_pred[27] = x265_intra_pred_ang4_27_avx2;
         p.cu[BLOCK_8x8].intra_pred[3] = x265_intra_pred_ang8_3_avx2;
         p.cu[BLOCK_8x8].intra_pred[33] = x265_intra_pred_ang8_33_avx2;
         p.cu[BLOCK_8x8].intra_pred[4] = x265_intra_pred_ang8_4_avx2;
diff -r 4750af9d9af4 -r aa58202ff26f source/common/x86/intrapred.h
--- a/source/common/x86/intrapred.h	Wed Apr 01 15:43:16 2015 +0530
+++ b/source/common/x86/intrapred.h	Wed Apr 01 17:06:42 2015 +0530
@@ -174,6 +174,7 @@
 DECL_ANG(32, 33, sse4);
 
 #undef DECL_ANG
+void x265_intra_pred_ang4_27_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
 void x265_intra_pred_ang8_3_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
 void x265_intra_pred_ang8_33_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
 void x265_intra_pred_ang8_4_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
diff -r 4750af9d9af4 -r aa58202ff26f source/common/x86/intrapred8.asm
--- a/source/common/x86/intrapred8.asm	Wed Apr 01 15:43:16 2015 +0530
+++ b/source/common/x86/intrapred8.asm	Wed Apr 01 17:06:42 2015 +0530
@@ -509,6 +509,12 @@
                  db 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2
                  db 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0
 
+
+ALIGN 32
+intra_pred_shuff_0_4:    times 4 db 0, 1, 1, 2, 2, 3, 3, 4
+
+c_ang4_mode_27:          db 30, 2, 30, 2, 30, 2, 30, 2, 28, 4, 28, 4, 28, 4, 28, 4, 26, 6, 26, 6, 26, 6, 26, 6, 24, 8, 24, 8, 24, 8, 24, 8
+
 ALIGN 32
 ;; (blkSize - 1 - x)
 pw_planar4_0:         dw 3,  2,  1,  0,  3,  2,  1,  0
@@ -15468,3 +15474,19 @@
     movu              [r0 + r3], m6
     RET
 %endif
+
+INIT_YMM avx2
+cglobal intra_pred_ang4_27, 3, 3, 1
+    vbroadcasti128    m0, [r2 + 1]
+    pshufb            m0, [intra_pred_shuff_0_4]
+    pmaddubsw         m0, [c_ang4_mode_27]
+    pmulhrsw          m0, [pw_1024]
+    packuswb          m0, m0
+
+    movd              [r0], xm0
+    pextrd            [r0 + r1], xm0, 1
+    vextracti128      xm0, m0, 1
+    lea               r0, [r0 + 2 * r1]
+    movd              [r0], xm0
+    pextrd            [r0 + r1], xm0, 1
+    RET