[x265] [PATCH 11 of 11] asm: reduce code size with macro 'INTRA_PRED_STORE_4x4'

praveen at multicorewareinc.com praveen at multicorewareinc.com
Thu Apr 2 12:49:45 CEST 2015


# HG changeset patch
# User Praveen Tiwari <praveen at multicorewareinc.com>
# Date 1427964379 -19800
#      Thu Apr 02 14:16:19 2015 +0530
# Node ID ace0d42bb35f0796eda0f2ba43c879f097de9e6b
# Parent  ed040fed39e74ab9b60e2a938c7e1aef52bbb8cb
asm: reduce code size with macro 'INTRA_PRED_STORE_4x4'

diff -r ed040fed39e7 -r ace0d42bb35f source/common/x86/intrapred8.asm
--- a/source/common/x86/intrapred8.asm	Thu Apr 02 14:08:10 2015 +0530
+++ b/source/common/x86/intrapred8.asm	Thu Apr 02 14:16:19 2015 +0530
@@ -15497,6 +15497,15 @@
     RET
 %endif
 
+%macro INTRA_PRED_STORE_4x4 0
+    movd              [r0], xm0
+    pextrd            [r0 + r1], xm0, 1
+    vextracti128      xm0, m0, 1
+    lea               r0, [r0 + 2 * r1]
+    movd              [r0], xm0
+    pextrd            [r0 + r1], xm0, 1
+%endmacro
+
 INIT_YMM avx2
 cglobal intra_pred_ang4_27, 3, 3, 1
     vbroadcasti128    m0, [r2 + 1]
@@ -15505,12 +15514,7 @@
     pmulhrsw          m0, [pw_1024]
     packuswb          m0, m0
 
-    movd              [r0], xm0
-    pextrd            [r0 + r1], xm0, 1
-    vextracti128      xm0, m0, 1
-    lea               r0, [r0 + 2 * r1]
-    movd              [r0], xm0
-    pextrd            [r0 + r1], xm0, 1
+    INTRA_PRED_STORE_4x4
     RET
 
 INIT_YMM avx2
@@ -15521,12 +15525,7 @@
     pmulhrsw          m0, [pw_1024]
     packuswb          m0, m0
 
-    movd              [r0], xm0
-    pextrd            [r0 + r1], xm0, 1
-    vextracti128      xm0, m0, 1
-    lea               r0, [r0 + 2 * r1]
-    movd              [r0], xm0
-    pextrd            [r0 + r1], xm0, 1
+    INTRA_PRED_STORE_4x4
     RET
 
 INIT_YMM avx2
@@ -15537,12 +15536,7 @@
     pmulhrsw          m0, [pw_1024]
     packuswb          m0, m0
 
-    movd              [r0], xm0
-    pextrd            [r0 + r1], xm0, 1
-    vextracti128      xm0, m0, 1
-    lea               r0, [r0 + 2 * r1]
-    movd              [r0], xm0
-    pextrd            [r0 + r1], xm0, 1
+    INTRA_PRED_STORE_4x4
     RET
 
 INIT_YMM avx2
@@ -15553,12 +15547,7 @@
     pmulhrsw          m0, [pw_1024]
     packuswb          m0, m0
 
-    movd              [r0], xm0
-    pextrd            [r0 + r1], xm0, 1
-    vextracti128      xm0, m0, 1
-    lea               r0, [r0 + 2 * r1]
-    movd              [r0], xm0
-    pextrd            [r0 + r1], xm0, 1
+    INTRA_PRED_STORE_4x4
     RET
 
 INIT_YMM avx2
@@ -15569,12 +15558,7 @@
     pmulhrsw          m0, [pw_1024]
     packuswb          m0, m0
 
-    movd              [r0], xm0
-    pextrd            [r0 + r1], xm0, 1
-    vextracti128      xm0, m0, 1
-    lea               r0, [r0 + 2 * r1]
-    movd              [r0], xm0
-    pextrd            [r0 + r1], xm0, 1
+    INTRA_PRED_STORE_4x4
     RET
 
 INIT_YMM avx2
@@ -15585,12 +15569,7 @@
     pmulhrsw          m0, [pw_1024]
     packuswb          m0, m0
 
-    movd              [r0], xm0
-    pextrd            [r0 + r1], xm0, 1
-    vextracti128      xm0, m0, 1
-    lea               r0, [r0 + 2 * r1]
-    movd              [r0], xm0
-    pextrd            [r0 + r1], xm0, 1
+    INTRA_PRED_STORE_4x4
     RET
 
 INIT_YMM avx2
@@ -15601,12 +15580,7 @@
     pmulhrsw          m0, [pw_1024]
     packuswb          m0, m0
 
-    movd              [r0], xm0
-    pextrd            [r0 + r1], xm0, 1
-    vextracti128      xm0, m0, 1
-    lea               r0, [r0 + 2 * r1]
-    movd              [r0], xm0
-    pextrd            [r0 + r1], xm0, 1
+    INTRA_PRED_STORE_4x4
     RET
 
 
@@ -15618,12 +15592,7 @@
     pmulhrsw          m0, [pw_1024]
     packuswb          m0, m0
 
-    movd              [r0], xm0
-    pextrd            [r0 + r1], xm0, 1
-    vextracti128      xm0, m0, 1
-    lea               r0, [r0 + 2 * r1]
-    movd              [r0], xm0
-    pextrd            [r0 + r1], xm0, 1
+    INTRA_PRED_STORE_4x4
     RET
 
 INIT_YMM avx2
@@ -15634,12 +15603,7 @@
     pmulhrsw          m0, [pw_1024]
     packuswb          m0, m0
 
-    movd              [r0], xm0
-    pextrd            [r0 + r1], xm0, 1
-    vextracti128      xm0, m0, 1
-    lea               r0, [r0 + 2 * r1]
-    movd              [r0], xm0
-    pextrd            [r0 + r1], xm0, 1
+    INTRA_PRED_STORE_4x4
     RET
 
 INIT_YMM avx2
@@ -15650,12 +15614,7 @@
     pmulhrsw          m0, [pw_1024]
     packuswb          m0, m0
 
-    movd              [r0], xm0
-    pextrd            [r0 + r1], xm0, 1
-    vextracti128      xm0, m0, 1
-    lea               r0, [r0 + 2 * r1]
-    movd              [r0], xm0
-    pextrd            [r0 + r1], xm0, 1
+    INTRA_PRED_STORE_4x4
     RET
 
 INIT_YMM avx2
@@ -15666,12 +15625,7 @@
     pmulhrsw          m0, [pw_1024]
     packuswb          m0, m0
 
-    movd              [r0], xm0
-    pextrd            [r0 + r1], xm0, 1
-    vextracti128      xm0, m0, 1
-    lea               r0, [r0 + 2 * r1]
-    movd              [r0], xm0
-    pextrd            [r0 + r1], xm0, 1
+    INTRA_PRED_STORE_4x4
     RET
 
 INIT_YMM avx2
@@ -15682,12 +15636,7 @@
     pmulhrsw          m0, [pw_1024]
     packuswb          m0, m0
 
-    movd              [r0], xm0
-    pextrd            [r0 + r1], xm0, 1
-    vextracti128      xm0, m0, 1
-    lea               r0, [r0 + 2 * r1]
-    movd              [r0], xm0
-    pextrd            [r0 + r1], xm0, 1
+    INTRA_PRED_STORE_4x4
     RET
 
 INIT_YMM avx2
@@ -15698,12 +15647,7 @@
     pmulhrsw          m0, [pw_1024]
     packuswb          m0, m0
 
-    movd              [r0], xm0
-    pextrd            [r0 + r1], xm0, 1
-    vextracti128      xm0, m0, 1
-    lea               r0, [r0 + 2 * r1]
-    movd              [r0], xm0
-    pextrd            [r0 + r1], xm0, 1
+    INTRA_PRED_STORE_4x4
     RET
 
 INIT_YMM avx2
@@ -15714,10 +15658,5 @@
     pmulhrsw          m0, [pw_1024]
     packuswb          m0, m0
 
-    movd              [r0], xm0
-    pextrd            [r0 + r1], xm0, 1
-    vextracti128      xm0, m0, 1
-    lea               r0, [r0 + 2 * r1]
-    movd              [r0], xm0
-    pextrd            [r0 + r1], xm0, 1
-    RET
+    INTRA_PRED_STORE_4x4
+    RET


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