[x265] [PATCH 02 of 18] asm: intra_pred_ang4_3_sse2 16-bit

[chen]

At 2015-04-04 00:24:33,dtyx265 at gmail.com wrote:
># HG changeset patch
># User David T Yuen <dtyx265 at gmail.com>
># Date 1428074312 25200
># Node ID 9bde344595ee60ea3beb9d09c839b897647f556f
># Parent  77edd96a4c1bc61d0bff30c4b2efef5bb8fbe2a1
>asm: intra_pred_ang4_3_sse2 16-bit
>
>This is backported from sse4 code and replaces c code.
>
>./test/TestBench --testbench intrapred | grep "intra_ang_4x4\[ 3\]"
>intra_ang_4x4[ 3]	3.65x 	 517.65   	 1888.27
>
>transposed mode 33
>
>./test/TestBench --testbench intrapred | grep "intra_ang_4x4\[33\]"
>intra_ang_4x4[33]	3.30x 	 412.82   	 1360.41
>
>diff -r 77edd96a4c1b -r 9bde344595ee source/common/x86/asm-primitives.cpp
>--- a/source/common/x86/asm-primitives.cpp	Fri Apr 03 07:56:12 2015 -0700
>+++ b/source/common/x86/asm-primitives.cpp	Fri Apr 03 08:18:32 2015 -0700
>@@ -883,6 +883,8 @@
>         p.cu[BLOCK_32x32].intra_pred[PLANAR_IDX] = x265_intra_pred_planar32_sse2;
> 
>         p.cu[BLOCK_4x4].intra_pred[2] = x265_intra_pred_ang4_2_sse2;
>+        p.cu[BLOCK_4x4].intra_pred[3] = x265_intra_pred_ang4_3_sse2;
>+        p.cu[BLOCK_4x4].intra_pred[33] = x265_intra_pred_ang4_3_sse2;
> 
>         p.cu[BLOCK_4x4].sse_ss = x265_pixel_ssd_ss_4x4_mmx2;
>         ALL_LUMA_CU(sse_ss, pixel_ssd_ss, sse2);
>diff -r 77edd96a4c1b -r 9bde344595ee source/common/x86/intrapred16.asm
>--- a/source/common/x86/intrapred16.asm	Fri Apr 03 07:56:12 2015 -0700
>+++ b/source/common/x86/intrapred16.asm	Fri Apr 03 08:18:32 2015 -0700
>@@ -712,6 +712,73 @@
>     movh        [r0 + r1],     m0
>     RET
> 
>+cglobal intra_pred_ang4_3, 3,5,8
>+    mov         r4d, 2
>+    cmp         r3m, byte 33
>+    mov         r3d, 18
>+    cmove       r3d, r4d
>+
>+    movu        m0, [r2 + r3]   ; [8 7 6 5 4 3 2 1]
>+
>+    mova        m2, m0
>+    psrldq      m0, 2
>+    punpcklwd   m2, m0      ; [5 4 4 3 3 2 2 1]
>+    mova        m3, m0
>+    psrldq      m0, 2
>+    punpcklwd   m3, m0      ; [6 5 5 4 4 3 3 2]
>+    mova        m4, m0
>+    psrldq      m0, 2
>+    punpcklwd   m4, m0      ; [7 6 6 5 5 4 4 3]
>+    mova        m5, m0
>+    psrldq      m0, 2
>+    punpcklwd   m5, m0      ; [8 7 7 6 6 5 5 4]
>+
>+
>+    lea         r3, [ang_table + 20 * 16]
>+    mova        m0, [r3 + 6 * 16]   ; [26]
>+    mova        m1, [r3]            ; [20]
>+    mova        m6, [r3 - 6 * 16]   ; [14]
>+    mova        m7, [r3 - 12 * 16]  ; [ 8]
>+    jmp        .do_filter4x4
>+
>+
>+ALIGN 16
>+.do_filter4x4:
>+    pmaddwd m2, m0
>+    paddd   m2, [pd_16]
r4 is free, buffer address may reduc code size

>+    psrld   m2, 5
>+
>+    pmaddwd m3, m1
>+    paddd   m3, [pd_16]
>+    psrld   m3, 5
>+    packssdw m2, m3
>+
>+    pmaddwd m4, m6
>+    paddd   m4, [pd_16]
>+    psrld   m4, 5
>+
>+    pmaddwd m5, m7
>+    paddd   m5, [pd_16]
>+    psrld   m5, 5
>+    packssdw m4, m5
>+
>+    jz         .store
>+
>+    ; transpose 4x4
>+    punpckhwd    m0, m2, m4
>+    punpcklwd    m2, m4
>+    punpckhwd    m4, m2, m0
>+    punpcklwd    m2, m0
>+
>+.store:
>+    add         r1, r1
>+    movh        [r0], m2
>+    movhps      [r0 + r1], m2
>+    movh        [r0 + r1 * 2], m4
>+    lea         r1, [r1 * 3]
>+    movhps      [r0 + r1], m4
>+    RET
>+
> ;-----------------------------------------------------------------------------------
> ; void intra_pred_dc(pixel* dst, intptr_t dstStride, pixel* above, int, int filter)
> ;-----------------------------------------------------------------------------------
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