[x265] [PATCH 1 of 4] asm: intra_pred_ang16_6 improved by ~19% over SSE4
praveen at multicorewareinc.com
praveen at multicorewareinc.com
Wed Apr 8 13:30:06 CEST 2015
# HG changeset patch
# User Praveen Tiwari <praveen at multicorewareinc.com>
# Date 1428472782 -19800
# Wed Apr 08 11:29:42 2015 +0530
# Node ID 230c8873db2929278c51ccaab959e3939d22a50f
# Parent 3e416dec8024b8339b18568cf65e48eb3448bed1
asm: intra_pred_ang16_6 improved by ~19% over SSE4
AVX2:
intra_ang_16x16[ 6] 14.04x 835.80 11734.08
SSE4:
intra_ang_16x16[ 6] 10.87x 1032.00 11222.11
diff -r 3e416dec8024 -r 230c8873db29 source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Tue Apr 07 16:00:39 2015 -0500
+++ b/source/common/x86/asm-primitives.cpp Wed Apr 08 11:29:42 2015 +0530
@@ -1761,6 +1761,7 @@
p.cu[BLOCK_8x8].intra_pred[12] = x265_intra_pred_ang8_12_avx2;
p.cu[BLOCK_8x8].intra_pred[24] = x265_intra_pred_ang8_24_avx2;
p.cu[BLOCK_8x8].intra_pred[11] = x265_intra_pred_ang8_11_avx2;
+ p.cu[BLOCK_16x16].intra_pred[6] = x265_intra_pred_ang16_6_avx2;
p.cu[BLOCK_16x16].intra_pred[7] = x265_intra_pred_ang16_7_avx2;
p.cu[BLOCK_16x16].intra_pred[8] = x265_intra_pred_ang16_8_avx2;
p.cu[BLOCK_16x16].intra_pred[9] = x265_intra_pred_ang16_9_avx2;
diff -r 3e416dec8024 -r 230c8873db29 source/common/x86/intrapred.h
--- a/source/common/x86/intrapred.h Tue Apr 07 16:00:39 2015 -0500
+++ b/source/common/x86/intrapred.h Wed Apr 08 11:29:42 2015 +0530
@@ -233,6 +233,7 @@
void x265_intra_pred_ang8_12_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
void x265_intra_pred_ang8_24_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
void x265_intra_pred_ang8_11_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
+void x265_intra_pred_ang16_6_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
void x265_intra_pred_ang16_7_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
void x265_intra_pred_ang16_8_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
void x265_intra_pred_ang16_9_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
diff -r 3e416dec8024 -r 230c8873db29 source/common/x86/intrapred8.asm
--- a/source/common/x86/intrapred8.asm Tue Apr 07 16:00:39 2015 -0500
+++ b/source/common/x86/intrapred8.asm Wed Apr 08 11:29:42 2015 +0530
@@ -210,6 +210,17 @@
db 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16
+
+ALIGN 32
+c_ang16_mode_6: db 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21
+ db 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2
+ db 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15
+ db 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28
+ db 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9
+ db 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22
+ db 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3
+ db 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16
+
ALIGN 32
c_ang16_mode_31: db 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17
db 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19
@@ -12055,7 +12066,91 @@
INTRA_PRED_TRANS_STORE_16x16
RET
-
+INIT_YMM avx2
+cglobal intra_pred_ang16_6, 3, 6, 12
+ mova m11, [pw_1024]
+ lea r5, [intra_pred_shuff_0_8]
+
+ movu xm9, [r2 + 1 + 32]
+ pshufb xm9, [r5]
+ movu xm10, [r2 + 9 + 32]
+ pshufb xm10, [r5]
+
+ movu xm7, [r2 + 4 + 32]
+ pshufb xm7, [r5]
+ vinserti128 m9, m9, xm7, 1
+
+ movu xm8, [r2 + 12 + 32]
+ pshufb xm8, [r5]
+ vinserti128 m10, m10, xm8, 1
+
+ lea r3, [3 * r1]
+ lea r4, [c_ang16_mode_6]
+
+ INTRA_PRED_ANG16_CAL_ROW m0, m1, 0
+
+ movu xm7, [r2 + 5 + 32]
+ pshufb xm7, [r5]
+ vinserti128 m9, m9, xm7, 1
+
+ movu xm8, [r2 + 13 + 32]
+ pshufb xm8, [r5]
+ vinserti128 m10, m10, xm8, 1
+
+ INTRA_PRED_ANG16_CAL_ROW m1, m2, 1
+
+ movu xm7, [r2 + 2 + 32]
+ pshufb xm7, [r5]
+ vinserti128 m9, m9, xm7, 0
+
+ movu xm8, [r2 + 10 + 32]
+ pshufb xm8, [r5]
+ vinserti128 m10, m10, xm8, 0
+
+ INTRA_PRED_ANG16_CAL_ROW m2, m3, 2
+ INTRA_PRED_ANG16_CAL_ROW m3, m4, 3
+
+ add r4, 4 * mmsize
+
+ movu xm9, [r2 + 3 + 32]
+ pshufb xm9, [r5]
+ movu xm10, [r2 + 11 + 32]
+ pshufb xm10, [r5]
+
+ movu xm7, [r2 + 6 + 32]
+ pshufb xm7, [r5]
+ vinserti128 m9, m9, xm7, 1
+
+ movu xm8, [r2 + 14 + 32]
+ pshufb xm8, [r5]
+ vinserti128 m10, m10, xm8, 1
+
+ INTRA_PRED_ANG16_CAL_ROW m4, m5, 0
+ INTRA_PRED_ANG16_CAL_ROW m5, m6, 1
+
+ movu xm7, [r2 + 7 + 32]
+ pshufb xm7, [r5]
+ vinserti128 m9, m9, xm7, 1
+
+ movu xm8, [r2 + 15 + 32]
+ pshufb xm8, [r5]
+ vinserti128 m10, m10, xm8, 1
+
+ INTRA_PRED_ANG16_CAL_ROW m6, m7, 2
+
+ movu xm7, [r2 + 4 + 32]
+ pshufb xm7, [r5]
+ vinserti128 m9, m9, xm7, 0
+
+ movu xm8, [r2 + 12 + 32]
+ pshufb xm8, [r5]
+ vinserti128 m10, m10, xm8, 0
+
+ INTRA_PRED_ANG16_CAL_ROW m7, m8, 3
+
+ ; transpose and store
+ INTRA_PRED_TRANS_STORE_16x16
+ RET
INIT_YMM avx2
cglobal intra_pred_ang16_7, 3, 6, 12
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