[x265] [PATCH 1 of 9] asm: intra_pred_ang16_12 improved by ~20% over SSE4
praveen at multicorewareinc.com
praveen at multicorewareinc.com
Thu Apr 9 15:20:09 CEST 2015
# HG changeset patch
# User Praveen Tiwari <praveen at multicorewareinc.com>
# Date 1428557307 -19800
# Thu Apr 09 10:58:27 2015 +0530
# Node ID 561f063f3ef9c65397c3f43ca84bcd51185f6ad4
# Parent 7f2d92923de47e7e40f04ff27ed70074b0dca9d3
asm: intra_pred_ang16_12 improved by ~20% over SSE4
AVX2:
intra_ang_16x16[12] 15.16x 777.51 11785.44
SSE4:
intra_ang_16x16[12] 11.51x 976.41 11238.16
diff -r 7f2d92923de4 -r 561f063f3ef9 source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Wed Apr 08 14:51:00 2015 -0500
+++ b/source/common/x86/asm-primitives.cpp Thu Apr 09 10:58:27 2015 +0530
@@ -1771,6 +1771,7 @@
p.cu[BLOCK_16x16].intra_pred[7] = x265_intra_pred_ang16_7_avx2;
p.cu[BLOCK_16x16].intra_pred[8] = x265_intra_pred_ang16_8_avx2;
p.cu[BLOCK_16x16].intra_pred[9] = x265_intra_pred_ang16_9_avx2;
+ p.cu[BLOCK_16x16].intra_pred[12] = x265_intra_pred_ang16_12_avx2;
p.cu[BLOCK_16x16].intra_pred[11] = x265_intra_pred_ang16_11_avx2;
p.cu[BLOCK_16x16].intra_pred[25] = x265_intra_pred_ang16_25_avx2;
p.cu[BLOCK_16x16].intra_pred[28] = x265_intra_pred_ang16_28_avx2;
diff -r 7f2d92923de4 -r 561f063f3ef9 source/common/x86/intrapred.h
--- a/source/common/x86/intrapred.h Wed Apr 08 14:51:00 2015 -0500
+++ b/source/common/x86/intrapred.h Thu Apr 09 10:58:27 2015 +0530
@@ -240,6 +240,7 @@
void x265_intra_pred_ang16_7_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
void x265_intra_pred_ang16_8_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
void x265_intra_pred_ang16_9_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
+void x265_intra_pred_ang16_12_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
void x265_intra_pred_ang16_11_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
void x265_intra_pred_ang16_25_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
void x265_intra_pred_ang16_28_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
diff -r 7f2d92923de4 -r 561f063f3ef9 source/common/x86/intrapred8.asm
--- a/source/common/x86/intrapred8.asm Wed Apr 08 14:51:00 2015 -0500
+++ b/source/common/x86/intrapred8.asm Thu Apr 09 10:58:27 2015 +0530
@@ -133,6 +133,17 @@
db 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2
db 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0
+
+ALIGN 32
+c_ang16_mode_12: db 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19
+ db 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14
+ db 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9
+ db 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4
+ db 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31
+ db 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26
+ db 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21
+ db 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16
+
ALIGN 32
c_ang16_mode_28: db 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10
db 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20
@@ -12066,6 +12077,65 @@
packuswb %1, %2
%endmacro
+
+INIT_YMM avx2
+cglobal intra_pred_ang16_12, 3, 5, 13
+ mova m11, [pw_1024]
+ lea r5, [intra_pred_shuff_0_8]
+
+ movu xm9, [r2 + 32]
+ pinsrb xm9, [r2], 0
+ pslldq xm7, xm9, 1
+ pinsrb xm7, [r2 + 6], 0
+ vinserti128 m9, m9, xm7, 1
+ pshufb m9, [r5]
+
+ movu xm12, [r2 + 6 + 32]
+
+ psrldq xm10, xm12, 2
+ psrldq xm8, xm12, 1
+ vinserti128 m10, m10, xm8, 1
+ pshufb m10, [r5]
+
+ lea r3, [3 * r1]
+ lea r4, [c_ang16_mode_12]
+
+ INTRA_PRED_ANG16_CAL_ROW m0, m1, 0
+ INTRA_PRED_ANG16_CAL_ROW m1, m2, 1
+ INTRA_PRED_ANG16_CAL_ROW m2, m3, 2
+ INTRA_PRED_ANG16_CAL_ROW m3, m4, 3
+
+ add r4, 4 * mmsize
+
+ pslldq xm7, 1
+ pinsrb xm7, [r2 + 13], 0
+ pshufb xm7, [r5]
+ vinserti128 m9, m9, xm7, 1
+
+ mova xm8, xm12
+ pshufb xm8, [r5]
+ vinserti128 m10, m10, xm8, 1
+
+ INTRA_PRED_ANG16_CAL_ROW m4, m5, 0
+ INTRA_PRED_ANG16_CAL_ROW m5, m6, 1
+
+ movu xm9, [r2 + 31]
+ pinsrb xm9, [r2 + 6], 0
+ pinsrb xm9, [r2 + 0], 1
+ pshufb xm9, [r5]
+ vinserti128 m9, m9, xm7, 1
+
+ psrldq xm10, xm12, 1
+ vinserti128 m10, m10, xm12, 1
+ pshufb m10, [r5]
+
+ INTRA_PRED_ANG16_CAL_ROW m6, m7, 2
+ INTRA_PRED_ANG16_CAL_ROW m7, m8, 3
+
+ ; transpose and store
+ INTRA_PRED_TRANS_STORE_16x16
+ RET
+
INIT_YMM avx2
cglobal intra_pred_ang16_11, 3, 5, 12
mova m11, [pw_1024]
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