[x265] [PATCH] asm: avx2 code for intra_ang_16 mode 6, replace old avx2 code

rajesh at multicorewareinc.com rajesh at multicorewareinc.com
Thu Aug 6 11:50:27 CEST 2015


# HG changeset patch
# User Rajesh Paulraj<rajesh at multicorewareinc.com>
# Date 1438850543 -19800
#      Thu Aug 06 14:12:23 2015 +0530
# Node ID 7195cd4420b97000a7ad7fb2a0861994223f5da4
# Parent  ac57cc4fedfc9fab8311a67a49e6c1c6259f6ec3
asm: avx2 code for intra_ang_16 mode 6, replace old avx2 code
with less constant table and 7% performance improvement

diff -r ac57cc4fedfc -r 7195cd4420b9 source/common/x86/intrapred8.asm
--- a/source/common/x86/intrapred8.asm	Thu Aug 06 13:14:07 2015 +0530
+++ b/source/common/x86/intrapred8.asm	Thu Aug 06 14:12:23 2015 +0530
@@ -236,18 +236,6 @@
                       db 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22
                       db 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16
 
-
-
-ALIGN 32
-c_ang16_mode_6:       db 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21
-                      db 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2
-                      db 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15
-                      db 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28
-                      db 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9
-                      db 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22
-                      db 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3
-                      db 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16
-
 ALIGN 32
 c_ang16_mode_31:      db 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17
                       db 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19
@@ -13889,95 +13877,97 @@
 
     call ang16_mode_5
     RET
+
+cglobal ang16_mode_6
+    ; rows 0 to 7
+    movu            m0,         [r2 +  1]           ; [32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1]
+    movu            m1,         [r2 +  2]           ; [33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2]
+
+    punpckhbw       m2,         m0, m1              ; [33 32 32 31 31 30 30 29 29 28 28 27 27 26 26 25 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10  9]
+    punpcklbw       m0,         m1                  ; [25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17  9  8  8  7  7  6  6  5  5  4  4  3  3  2  2  1]
+    vextracti128    xm1,        m0, 1
+    vperm2i128      m0,         m0, m2, 0x20        ; [17 16 16 15 15 14 14 13 13 12 12 11 11 10 10  9  9  8  8  7  7  6  6  5  5  4  4  3  3  2  2  1]
+    vperm2i128      m2,         m2, m1, 0x20        ; [25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10  9]
+
+    pmaddubsw       m4,         m0, [r3 - 3 * 32]   ; [13]
+    pmulhrsw        m4,         m7
+
+    pmaddubsw       m5,         m0, [r3 + 10 * 32]  ; [26]
+    pmulhrsw        m5,         m7
+
+    palignr         m3,         m2, m0, 2
+    pmaddubsw       m6,         m3, [r3 - 9 * 32]   ; [7]
+    pmulhrsw        m6,         m7
+    pmaddubsw       m8,         m3, [r3 + 4 * 32]   ; [20]
+    pmulhrsw        m8,         m7
+
+    palignr         m3,         m2, m0, 4
+    pmaddubsw       m9,         m3, [r3 - 15 * 32]  ; [1]
+    pmulhrsw        m9,         m7
+
+    pmaddubsw       m10,        m3, [r3 - 2 * 32]   ; [14]
+    pmulhrsw        m10,        m7
+
+    pmaddubsw       m11,        m3, [r3 + 11 * 32]  ; [27]
+    pmulhrsw        m11,        m7
+
+    palignr         m1,         m2, m0, 6
+    pmaddubsw       m12,        m1, [r3 - 8 * 32]   ; [8]
+    pmulhrsw        m12,        m7
+
+    ; rows 8 to 15
+    pmaddubsw       m3,         m1, [r3 + 5 * 32]   ; [21]
+    pmulhrsw        m3,         m7
+    packuswb        m4,         m3
+
+    palignr         m1,         m2, m0, 8
+    pmaddubsw       m3,         m1, [r3 - 14 * 32]  ; [2]
+    pmulhrsw        m3,         m7
+    packuswb        m5,         m3
+
+    pmaddubsw       m3,         m1, [r3 - 1 * 32]   ; [15]
+    pmulhrsw        m3,         m7
+    packuswb        m6,         m3
+
+    pmaddubsw       m3,         m1, [r3 + 12 * 32]  ; [28]
+    pmulhrsw        m3,         m7
+    packuswb        m8,         m3
+
+    palignr         m1,         m2, m0, 10
+    pmaddubsw       m3,         m1, [r3 - 7 * 32]   ; [9]
+    pmulhrsw        m3,         m7
+    packuswb        m9,         m3
+
+    pmaddubsw       m3,         m1, [r3 + 6 * 32]   ; [22]
+    pmulhrsw        m3,         m7
+    packuswb        m10,        m3
+
+    palignr         m1,         m2, m0, 12
+    pmaddubsw       m3,         m1, [r3 - 13 * 32]  ; [3]
+    pmulhrsw        m3,         m7
+    packuswb        m11,        m3
+
+    pmaddubsw       m1,         [r3]                ; [16]
+    pmulhrsw        m1,         m7
+    packuswb        m12,        m1
+
+    TRANSPOSE_STORE_8x32 4, 5, 6, 8, 9, 10, 11, 12, 0, 1, 2, 3
+    ret
+
+INIT_YMM avx2
+cglobal intra_pred_ang16_6, 3, 7, 13
+    add             r2, 32
+    lea             r3, [ang_table_avx2 + 16 * 32]
+    lea             r5, [r1 * 3]       ; r5 -> 3 * stride
+    lea             r6, [r1 * 4]       ; r6 -> 4 * stride
+    mova            m7, [pw_1024]
+    clc
+
+    call ang16_mode_6
+    RET
 %endif  ; ARCH_X86_64
 
 INIT_YMM avx2
-cglobal intra_pred_ang16_6, 3, 6, 12
-    mova              m11, [pw_1024]
-    lea               r5, [intra_pred_shuff_0_8]
-
-    movu              xm9, [r2 + 1 + 32]
-    pshufb            xm9, [r5]
-    movu              xm10, [r2 + 9 + 32]
-    pshufb            xm10, [r5]
-
-    movu              xm7, [r2 + 4 + 32]
-    pshufb            xm7, [r5]
-    vinserti128       m9, m9, xm7, 1
-
-    movu              xm8, [r2 + 12 + 32]
-    pshufb            xm8, [r5]
-    vinserti128       m10, m10, xm8, 1
-
-    lea               r3, [3 * r1]
-    lea               r4, [c_ang16_mode_6]
-
-    INTRA_PRED_ANG16_CAL_ROW m0, m1, 0
-
-    movu              xm7, [r2 + 5 + 32]
-    pshufb            xm7, [r5]
-    vinserti128       m9, m9, xm7, 1
-
-    movu              xm8, [r2 + 13 + 32]
-    pshufb            xm8, [r5]
-    vinserti128       m10, m10, xm8, 1
-
-    INTRA_PRED_ANG16_CAL_ROW m1, m2, 1
-
-    movu              xm7, [r2 + 2 + 32]
-    pshufb            xm7, [r5]
-    vinserti128       m9, m9, xm7, 0
-
-    movu              xm8, [r2 + 10 + 32]
-    pshufb            xm8, [r5]
-    vinserti128       m10, m10, xm8, 0
-
-    INTRA_PRED_ANG16_CAL_ROW m2, m3, 2
-    INTRA_PRED_ANG16_CAL_ROW m3, m4, 3
-
-    add               r4, 4 * mmsize
-
-    movu              xm9, [r2 + 3 + 32]
-    pshufb            xm9, [r5]
-    movu              xm10, [r2 + 11 + 32]
-    pshufb            xm10, [r5]
-
-    movu              xm7, [r2 + 6 + 32]
-    pshufb            xm7, [r5]
-    vinserti128       m9, m9, xm7, 1
-
-    movu              xm8, [r2 + 14 + 32]
-    pshufb            xm8, [r5]
-    vinserti128       m10, m10, xm8, 1
-
-    INTRA_PRED_ANG16_CAL_ROW m4, m5, 0
-    INTRA_PRED_ANG16_CAL_ROW m5, m6, 1
-
-    movu              xm7, [r2 + 7 + 32]
-    pshufb            xm7, [r5]
-    vinserti128       m9, m9, xm7, 1
-
-    movu              xm8, [r2 + 15 + 32]
-    pshufb            xm8, [r5]
-    vinserti128       m10, m10, xm8, 1
-
-    INTRA_PRED_ANG16_CAL_ROW m6, m7, 2
-
-    movu              xm7, [r2 + 4 + 32]
-    pshufb            xm7, [r5]
-    vinserti128       m9, m9, xm7, 0
-
-    movu              xm8, [r2 + 12 + 32]
-    pshufb            xm8, [r5]
-    vinserti128       m10, m10, xm8, 0
-
-    INTRA_PRED_ANG16_CAL_ROW m7, m8, 3
-
-    ; transpose and store
-    INTRA_PRED_TRANS_STORE_16x16
-    RET
-
-INIT_YMM avx2
 cglobal intra_pred_ang16_7, 3, 6, 12
     mova              m11, [pw_1024]
     lea               r5, [intra_pred_shuff_0_8]


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