[x265] [PATCH 5 of 7] asm: avx2 asm for intra_ang32 mode 12, 4758c->1474c

dnyaneshwar at multicorewareinc.com dnyaneshwar at multicorewareinc.com
Wed Aug 26 12:24:34 CEST 2015


# HG changeset patch
# User Dnyaneshwar G <dnyaneshwar at multicorewareinc.com>
# Date 1440583211 -19800
#      Wed Aug 26 15:30:11 2015 +0530
# Node ID cb3f520f9942080d05ca1b3ba2cae0c1b4bcb345
# Parent  a27ac3b998f5677570a48285d22e1b771c08ab75
asm: avx2 asm for intra_ang32 mode 12, 4758c->1474c
updated intra_ang_32 mode 25 AVX2 asm code, improved 1438c->1270c

diff -r a27ac3b998f5 -r cb3f520f9942 source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp	Tue Aug 25 11:02:17 2015 +0530
+++ b/source/common/x86/asm-primitives.cpp	Wed Aug 26 15:30:11 2015 +0530
@@ -3000,6 +3000,7 @@
         p.cu[BLOCK_32x32].intra_pred[9]  = PFX(intra_pred_ang32_9_avx2);
         p.cu[BLOCK_32x32].intra_pred[10] = PFX(intra_pred_ang32_10_avx2);
         p.cu[BLOCK_32x32].intra_pred[11] = PFX(intra_pred_ang32_11_avx2);
+        p.cu[BLOCK_32x32].intra_pred[12] = PFX(intra_pred_ang32_12_avx2);
         p.cu[BLOCK_32x32].intra_pred[34] = PFX(intra_pred_ang32_34_avx2);
         p.cu[BLOCK_32x32].intra_pred[2] = PFX(intra_pred_ang32_2_avx2);
         p.cu[BLOCK_32x32].intra_pred[26] = PFX(intra_pred_ang32_26_avx2);
diff -r a27ac3b998f5 -r cb3f520f9942 source/common/x86/intrapred8.asm
--- a/source/common/x86/intrapred8.asm	Tue Aug 25 11:02:17 2015 +0530
+++ b/source/common/x86/intrapred8.asm	Wed Aug 26 15:30:11 2015 +0530
@@ -262,26 +262,6 @@
                      db 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16
 
 ALIGN 32
-c_ang32_mode_24:   db 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22
-                   db 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12
-                   db 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2
-                   db 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24
-                   db 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14
-                   db 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4
-                   db 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26
-                   db 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16
-                   db 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6
-                   db 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1
-                   db 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23
-                   db 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13
-                   db 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3
-                   db 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25
-                   db 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15
-                   db 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5
-                   db 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0
-
-
-ALIGN 32
 c_ang32_mode_23:  db 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14
                   db 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5
                   db 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19
@@ -494,6 +474,15 @@
 const ang32_shuf_mode11,        times 8 db 1, 2
                                 times 8 db 0, 1
 
+const ang32_fact_mode12,        db (32-27), 27, (32-22), 22, (32-17), 17, (32-12), 12, (32- 7),  7, (32- 2),  2, (32-29), 29, (32-24), 24
+                                db (32-11), 11, (32- 6),  6, (32- 1),  1, (32-28), 28, (32-23), 23, (32-18), 18, (32-13), 13, (32- 8),  8
+                                db (32-19), 19, (32-14), 14, (32- 9),  9, (32- 4),  4, (32-31), 31, (32-26), 26, (32-21), 21, (32-16), 16
+                                db (32- 3),  3, (32-30), 30, (32-25), 25, (32-20), 20, (32-15), 15, (32-10), 10, (32- 5),  5, (32- 0),  0
+const ang32_shuf_mode12,        db  4,  5,  4,  5,  4,  5,  4,  5,  4,  5,  4,  5,  3,  4,  3,  4,  2,  3,  2,  3,  2,  3,  1,  2,  1,  2,  1,  2,  1,  2,  1,  2
+                                db  3,  4,  3,  4,  3,  4,  3,  4,  2,  3,  2,  3,  2,  3,  2,  3,  1,  2,  0,  1,  0,  1,  0,  1,  0,  1,  0,  1,  0,  1,  0,  1
+const ang32_shuf_mode24,        db  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0, 13, 13,  6,  6,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0, 10, 10,  3,  3
+                                dd  0,  0,  7,  3,  0,  0,  7,  3
+
 const ang_table
 %assign x 0
 %rep 32
@@ -14577,6 +14566,631 @@
     movu                [r0 + r4], m1
     RET
 
+cglobal intra_pred_ang32_12, 3,4,9
+    movu                m0, [ang32_fact_mode12]
+    movu                m1, [ang32_fact_mode12 + mmsize]
+    mova                m2, [pw_1024]
+    mova                m7, [ang32_shuf_mode12]
+    mova                m8, [ang32_shuf_mode12 + mmsize]
+    lea                 r3, [r1 * 3]
+
+    ; prepare for [26, 19, 13,  6,  0, -1, -2....]
+
+    movu               xm4, [r2 + mmsize*2 - 4]
+    vbroadcasti128      m6, [r2 + mmsize*2 + 12]
+
+    pinsrb             xm4, [r2 +  0], 4
+    pinsrb             xm4, [r2 +  6], 3
+    pinsrb             xm4, [r2 + 13], 2
+    pinsrb             xm4, [r2 + 19], 1
+    pinsrb             xm4, [r2 + 26], 0
+    vinserti128         m3, m4, xm4, 1      ; [26, 19, 13,  6,  0,  1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 26, 19, 13,  6,  0,  1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11]
+
+    pshufb              m4, m3, m7          ; [ 0,  1,  0,  1,  0,  1,  0,  1,  0,  1,  0,  1,  6,  0,  6,  0, 13,  6, 13,  6, 13,  6, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13]
+    pshufb              m5, m3, m8          ; [ 6,  0,  6,  0,  6,  0,  6,  0, 13,  6, 13,  6, 13,  6, 13,  6, 19, 13, 16, 19, 16, 19, 16, 19, 16, 19, 16, 19, 16, 19, 16, 19]
+    pmaddubsw           m4, m0
+    pmaddubsw           m5, m1
+    pmulhrsw            m4, m2
+    pmulhrsw            m5, m2
+    packuswb            m4, m5
+    movu                [r0], m4
+
+    palignr             m4, m6, m3, 1
+    pshufb              m5, m4, m8
+    pshufb              m4, m7
+    pmaddubsw           m4, m0
+    pmaddubsw           m5, m1
+    pmulhrsw            m4, m2
+    pmulhrsw            m5, m2
+    packuswb            m4, m5
+    movu                [r0 + r1], m4
+
+    palignr             m4, m6, m3, 2
+    pshufb              m5, m4, m8
+    pshufb              m4, m7
+    pmaddubsw           m4, m0
+    pmaddubsw           m5, m1
+    pmulhrsw            m4, m2
+    pmulhrsw            m5, m2
+    packuswb            m4, m5
+    movu                [r0 + r1 * 2], m4
+
+    palignr             m4, m6, m3, 3
+    pshufb              m5, m4, m8
+    pshufb              m4, m7
+    pmaddubsw           m4, m0
+    pmaddubsw           m5, m1
+    pmulhrsw            m4, m2
+    pmulhrsw            m5, m2
+    packuswb            m4, m5
+    movu                [r0 + r3], m4
+
+    lea                 r0, [r0 + r1 * 4]
+
+    palignr             m4, m6, m3, 4
+    pshufb              m5, m4, m8
+    pshufb              m4, m7
+    pmaddubsw           m4, m0
+    pmaddubsw           m5, m1
+    pmulhrsw            m4, m2
+    pmulhrsw            m5, m2
+    packuswb            m4, m5
+    movu                [r0], m4
+
+    palignr             m4, m6, m3, 5
+    pshufb              m5, m4, m8
+    pshufb              m4, m7
+    pmaddubsw           m4, m0
+    pmaddubsw           m5, m1
+    pmulhrsw            m4, m2
+    pmulhrsw            m5, m2
+    packuswb            m4, m5
+    movu                [r0 + r1], m4
+
+    palignr             m4, m6, m3, 6
+    pshufb              m5, m4, m8
+    pshufb              m4, m7
+    pmaddubsw           m4, m0
+    pmaddubsw           m5, m1
+    pmulhrsw            m4, m2
+    pmulhrsw            m5, m2
+    packuswb            m4, m5
+    movu                [r0 + r1 * 2], m4
+
+    palignr             m4, m6, m3, 7
+    pshufb              m5, m4, m8
+    pshufb              m4, m7
+    pmaddubsw           m4, m0
+    pmaddubsw           m5, m1
+    pmulhrsw            m4, m2
+    pmulhrsw            m5, m2
+    packuswb            m4, m5
+    movu                [r0 + r3], m4
+
+    lea                 r0, [r0 + r1 * 4]
+
+    palignr             m4, m6, m3, 8
+    pshufb              m5, m4, m8
+    pshufb              m4, m7
+    pmaddubsw           m4, m0
+    pmaddubsw           m5, m1
+    pmulhrsw            m4, m2
+    pmulhrsw            m5, m2
+    packuswb            m4, m5
+    movu                [r0], m4
+
+    palignr             m4, m6, m3, 9
+    pshufb              m5, m4, m8
+    pshufb              m4, m7
+    pmaddubsw           m4, m0
+    pmaddubsw           m5, m1
+    pmulhrsw            m4, m2
+    pmulhrsw            m5, m2
+    packuswb            m4, m5
+    movu                [r0 + r1], m4
+
+    palignr             m4, m6, m3, 10
+    pshufb              m5, m4, m8
+    pshufb              m4, m7
+    pmaddubsw           m4, m0
+    pmaddubsw           m5, m1
+    pmulhrsw            m4, m2
+    pmulhrsw            m5, m2
+    packuswb            m4, m5
+    movu                [r0 + r1 * 2], m4
+
+    palignr             m4, m6, m3, 11
+    pshufb              m5, m4, m8
+    pshufb              m4, m7
+    pmaddubsw           m4, m0
+    pmaddubsw           m5, m1
+    pmulhrsw            m4, m2
+    pmulhrsw            m5, m2
+    packuswb            m4, m5
+    movu                [r0 + r3], m4
+
+    lea                 r0, [r0 + r1 * 4]
+
+    palignr             m4, m6, m3, 12
+    pshufb              m5, m4, m8
+    pshufb              m4, m7
+    pmaddubsw           m4, m0
+    pmaddubsw           m5, m1
+    pmulhrsw            m4, m2
+    pmulhrsw            m5, m2
+    packuswb            m4, m5
+    movu                [r0], m4
+
+    palignr             m4, m6, m3, 13
+    pshufb              m5, m4, m8
+    pshufb              m4, m7
+    pmaddubsw           m4, m0
+    pmaddubsw           m5, m1
+    pmulhrsw            m4, m2
+    pmulhrsw            m5, m2
+    packuswb            m4, m5
+    movu                [r0 + r1], m4
+
+    palignr             m4, m6, m3, 14
+    pshufb              m5, m4, m8
+    pshufb              m4, m7
+    pmaddubsw           m4, m0
+    pmaddubsw           m5, m1
+    pmulhrsw            m4, m2
+    pmulhrsw            m5, m2
+    packuswb            m4, m5
+    movu                [r0 + r1 * 2], m4
+
+    palignr             m4, m6, m3, 15
+    pshufb              m5, m4, m8
+    pshufb              m4, m7
+    pmaddubsw           m4, m0
+    pmaddubsw           m5, m1
+    pmulhrsw            m4, m2
+    pmulhrsw            m5, m2
+    packuswb            m4, m5
+    movu                [r0 + r3], m4
+
+    lea                 r0, [r0 + r1 * 4]
+    mova                m3, m6
+    vbroadcasti128      m6, [r2 + mmsize*2 + 12 + 16]
+
+    pshufb              m4, m3, m7
+    pshufb              m5, m3, m8
+    pmaddubsw           m4, m0
+    pmaddubsw           m5, m1
+    pmulhrsw            m4, m2
+    pmulhrsw            m5, m2
+    packuswb            m4, m5
+    movu                [r0], m4
+
+    palignr             m4, m6, m3, 1
+    pshufb              m5, m4, m8
+    pshufb              m4, m7
+    pmaddubsw           m4, m0
+    pmaddubsw           m5, m1
+    pmulhrsw            m4, m2
+    pmulhrsw            m5, m2
+    packuswb            m4, m5
+    movu                [r0 + r1], m4
+
+    palignr             m4, m6, m3, 2
+    pshufb              m5, m4, m8
+    pshufb              m4, m7
+    pmaddubsw           m4, m0
+    pmaddubsw           m5, m1
+    pmulhrsw            m4, m2
+    pmulhrsw            m5, m2
+    packuswb            m4, m5
+    movu                [r0 + r1 * 2], m4
+
+    palignr             m4, m6, m3, 3
+    pshufb              m5, m4, m8
+    pshufb              m4, m7
+    pmaddubsw           m4, m0
+    pmaddubsw           m5, m1
+    pmulhrsw            m4, m2
+    pmulhrsw            m5, m2
+    packuswb            m4, m5
+    movu                [r0 + r3], m4
+
+    lea                 r0, [r0 + r1 * 4]
+
+    palignr             m4, m6, m3, 4
+    pshufb              m5, m4, m8
+    pshufb              m4, m7
+    pmaddubsw           m4, m0
+    pmaddubsw           m5, m1
+    pmulhrsw            m4, m2
+    pmulhrsw            m5, m2
+    packuswb            m4, m5
+    movu                [r0], m4
+
+    palignr             m4, m6, m3, 5
+    pshufb              m5, m4, m8
+    pshufb              m4, m7
+    pmaddubsw           m4, m0
+    pmaddubsw           m5, m1
+    pmulhrsw            m4, m2
+    pmulhrsw            m5, m2
+    packuswb            m4, m5
+    movu                [r0 + r1], m4
+
+    palignr             m4, m6, m3, 6
+    pshufb              m5, m4, m8
+    pshufb              m4, m7
+    pmaddubsw           m4, m0
+    pmaddubsw           m5, m1
+    pmulhrsw            m4, m2
+    pmulhrsw            m5, m2
+    packuswb            m4, m5
+    movu                [r0 + r1 * 2], m4
+
+    palignr             m4, m6, m3, 7
+    pshufb              m5, m4, m8
+    pshufb              m4, m7
+    pmaddubsw           m4, m0
+    pmaddubsw           m5, m1
+    pmulhrsw            m4, m2
+    pmulhrsw            m5, m2
+    packuswb            m4, m5
+    movu                [r0 + r3], m4
+
+    lea                 r0, [r0 + r1 * 4]
+
+    palignr             m4, m6, m3, 8
+    pshufb              m5, m4, m8
+    pshufb              m4, m7
+    pmaddubsw           m4, m0
+    pmaddubsw           m5, m1
+    pmulhrsw            m4, m2
+    pmulhrsw            m5, m2
+    packuswb            m4, m5
+    movu                [r0], m4
+
+    palignr             m4, m6, m3, 9
+    pshufb              m5, m4, m8
+    pshufb              m4, m7
+    pmaddubsw           m4, m0
+    pmaddubsw           m5, m1
+    pmulhrsw            m4, m2
+    pmulhrsw            m5, m2
+    packuswb            m4, m5
+    movu                [r0 + r1], m4
+
+    palignr             m4, m6, m3, 10
+    pshufb              m5, m4, m8
+    pshufb              m4, m7
+    pmaddubsw           m4, m0
+    pmaddubsw           m5, m1
+    pmulhrsw            m4, m2
+    pmulhrsw            m5, m2
+    packuswb            m4, m5
+    movu                [r0 + r1 * 2], m4
+
+    palignr             m4, m6, m3, 11
+    pshufb              m5, m4, m8
+    pshufb              m4, m7
+    pmaddubsw           m4, m0
+    pmaddubsw           m5, m1
+    pmulhrsw            m4, m2
+    pmulhrsw            m5, m2
+    packuswb            m4, m5
+    movu                [r0 + r3], m4
+
+    lea                 r0, [r0 + r1 * 4]
+
+    palignr             m4, m6, m3, 12
+    pshufb              m5, m4, m8
+    pshufb              m4, m7
+    pmaddubsw           m4, m0
+    pmaddubsw           m5, m1
+    pmulhrsw            m4, m2
+    pmulhrsw            m5, m2
+    packuswb            m4, m5
+    movu                [r0], m4
+
+    palignr             m4, m6, m3, 13
+    pshufb              m5, m4, m8
+    pshufb              m4, m7
+    pmaddubsw           m4, m0
+    pmaddubsw           m5, m1
+    pmulhrsw            m4, m2
+    pmulhrsw            m5, m2
+    packuswb            m4, m5
+    movu                [r0 + r1], m4
+
+    palignr             m4, m6, m3, 14
+    pshufb              m5, m4, m8
+    pshufb              m4, m7
+    pmaddubsw           m4, m0
+    pmaddubsw           m5, m1
+    pmulhrsw            m4, m2
+    pmulhrsw            m5, m2
+    packuswb            m4, m5
+    movu                [r0 + r1 * 2], m4
+
+    palignr             m4, m6, m3, 15
+    pshufb              m5, m4, m8
+    pshufb              m4, m7
+    pmaddubsw           m4, m0
+    pmaddubsw           m5, m1
+    pmulhrsw            m4, m2
+    pmulhrsw            m5, m2
+    packuswb            m4, m5
+    movu                [r0 + r3], m4
+    RET
+
+cglobal intra_pred_ang32_24, 3,5,8
+    lea                 r3, [ang_table_avx2 + 32 * 16]
+    lea                 r4, [r1 * 3]
+    mova                m5, [pw_1024]
+
+    ; rows 0 to 7
+    movu                m0, [r2 + 0]
+    movu                m1, [r2 + 1]
+    punpckhbw           m2, m0, m1
+    punpcklbw           m0, m1
+
+    movu                m4, [r2 + mmsize*2]
+    pshufb              m4, [ang32_shuf_mode24]
+    mova                m3, [ang32_shuf_mode24 + mmsize]
+    vpermd              m4, m3, m4                      ; [6  6 13 13 19 19 26 26 x x x...]
+    palignr             m3, m0, m4, 1
+    vinserti128         m3, m3, xm2, 1
+
+    pmaddubsw           m4, m0, [r3 + 11 * 32]          ; [27]
+    pmulhrsw            m4, m5
+    pmaddubsw           m1, m2, [r3 + 11 * 32]
+    pmulhrsw            m1, m5
+    packuswb            m4, m1
+    movu                [r0], m4
+
+    pmaddubsw           m4, m0, [r3 + 6 * 32]           ; [22]
+    pmulhrsw            m4, m5
+    pmaddubsw           m1, m2, [r3 + 6 * 32]
+    pmulhrsw            m1, m5
+    packuswb            m4, m1
+    movu                [r0 + r1], m4
+
+    pmaddubsw           m4, m0, [r3 + 1 * 32]           ; [17]
+    pmulhrsw            m4, m5
+    pmaddubsw           m1, m2, [r3 + 1 * 32]
+    pmulhrsw            m1, m5
+    packuswb            m4, m1
+    movu                [r0 + r1*2], m4
+
+    pmaddubsw           m4, m0, [r3 - 4 * 32]           ; [12]
+    pmulhrsw            m4, m5
+    pmaddubsw           m1, m2, [r3 - 4 * 32]
+    pmulhrsw            m1, m5
+    packuswb            m4, m1
+    movu                [r0 + r4], m4
+
+    lea                 r0, [r0 + r1 * 4]
+
+    pmaddubsw           m4, m0, [r3 - 9 * 32]           ; [7]
+    pmulhrsw            m4, m5
+    pmaddubsw           m1, m2, [r3 - 9 * 32]
+    pmulhrsw            m1, m5
+    packuswb            m4, m1
+    movu                [r0], m4
+
+    pmaddubsw           m4, m0, [r3 - 14 * 32]          ; [2]
+    pmulhrsw            m4, m5
+    pmaddubsw           m1, m2, [r3 - 14 * 32]
+    pmulhrsw            m1, m5
+    packuswb            m4, m1
+    movu                [r0 + r1], m4
+
+    palignr             m6, m0, m3, 14
+    palignr             m7, m2, m0, 14
+
+    pmaddubsw           m4, m6, [r3 + 13 * 32]          ; [29]
+    pmulhrsw            m4, m5
+    pmaddubsw           m1, m7, [r3 + 13 * 32]
+    pmulhrsw            m1, m5
+    packuswb            m4, m1
+    movu                [r0 + r1*2], m4
+
+    pmaddubsw           m4, m6, [r3 + 8 * 32]           ; [24]
+    pmulhrsw            m4, m5
+    pmaddubsw           m1, m7, [r3 + 8 * 32]
+    pmulhrsw            m1, m5
+    packuswb            m4, m1
+    movu                [r0 + r4], m4
+
+    lea                 r0, [r0 + r1 * 4]
+
+    ; rows 8 to 15
+    pmaddubsw           m4, m6, [r3 + 3 * 32]           ; [19]
+    pmulhrsw            m4, m5
+    pmaddubsw           m1, m7, [r3 + 3 * 32]
+    pmulhrsw            m1, m5
+    packuswb            m4, m1
+    movu                [r0], m4
+
+    pmaddubsw           m4, m6, [r3 - 2 * 32]           ; [14]
+    pmulhrsw            m4, m5
+    pmaddubsw           m1, m7, [r3 - 2 * 32]
+    pmulhrsw            m1, m5
+    packuswb            m4, m1
+    movu                [r0 + r1], m4
+
+    pmaddubsw           m4, m6, [r3 - 7 * 32]           ; [9]
+    pmulhrsw            m4, m5
+    pmaddubsw           m1, m7, [r3 - 7 * 32]
+    pmulhrsw            m1, m5
+    packuswb            m4, m1
+    movu                [r0 + r1*2], m4
+
+    pmaddubsw           m4, m6, [r3 - 12 * 32]          ; [4]
+    pmulhrsw            m4, m5
+    pmaddubsw           m1, m7, [r3 - 12 * 32]
+    pmulhrsw            m1, m5
+    packuswb            m4, m1
+    movu                [r0 + r4], m4
+
+    lea                 r0, [r0 + r1 * 4]
+
+    palignr             m6, m0, m3, 12
+    palignr             m7, m2, m0, 12
+
+    pmaddubsw           m4, m6, [r3 + 15 * 32]          ; [31]
+    pmulhrsw            m4, m5
+    pmaddubsw           m1, m7, [r3 + 15 * 32]
+    pmulhrsw            m1, m5
+    packuswb            m4, m1
+    movu                [r0], m4
+
+    pmaddubsw           m4, m6, [r3 + 10 * 32]          ; [26]
+    pmulhrsw            m4, m5
+    pmaddubsw           m1, m7, [r3 + 10 * 32]
+    pmulhrsw            m1, m5
+    packuswb            m4, m1
+    movu                [r0 + r1], m4
+
+    pmaddubsw           m4, m6, [r3 + 5 * 32]           ; [21]
+    pmulhrsw            m4, m5
+    pmaddubsw           m1, m7, [r3 + 5 * 32]
+    pmulhrsw            m1, m5
+    packuswb            m4, m1
+    movu                [r0 + r1 * 2], m4
+
+    pmaddubsw           m4, m6, [r3]                    ; [16]
+    pmulhrsw            m4, m5
+    pmaddubsw           m1, m7, [r3]
+    pmulhrsw            m1, m5
+    packuswb            m4, m1
+    movu                [r0 + r4], m4
+
+    lea                 r0, [r0 + r1 * 4]
+
+    ; rows 16 to 23
+    pmaddubsw           m4, m6, [r3 - 5 * 32]           ; [11]
+    pmulhrsw            m4, m5
+    pmaddubsw           m1, m7, [r3 - 5 * 32]
+    pmulhrsw            m1, m5
+    packuswb            m4, m1
+    movu                [r0], m4
+
+    pmaddubsw           m4, m6, [r3 - 10 * 32]          ; [6]
+    pmulhrsw            m4, m5
+    pmaddubsw           m1, m7, [r3 - 10 * 32]
+    pmulhrsw            m1, m5
+    packuswb            m4, m1
+    movu                [r0 + r1], m4
+
+    pmaddubsw           m4, m6, [r3 - 15 * 32]          ; [1]
+    pmulhrsw            m4, m5
+    pmaddubsw           m1, m7, [r3 - 15 * 32]
+    pmulhrsw            m1, m5
+    packuswb            m4, m1
+    movu                [r0 + r1*2], m4
+
+    palignr             m6, m0, m3, 10
+    palignr             m7, m2, m0, 10
+
+    pmaddubsw           m4, m6, [r3 + 12 * 32]          ; [28]
+    pmulhrsw            m4, m5
+    pmaddubsw           m1, m7, [r3 + 12 * 32]
+    pmulhrsw            m1, m5
+    packuswb            m4, m1
+    movu                [r0 + r4], m4
+
+    lea                 r0, [r0 + r1 * 4]
+
+    pmaddubsw           m4, m6, [r3 + 7 * 32]           ; [23]
+    pmulhrsw            m4, m5
+    pmaddubsw           m1, m7, [r3 + 7 * 32]
+    pmulhrsw            m1, m5
+    packuswb            m4, m1
+    movu                [r0], m4
+
+    pmaddubsw           m4, m6, [r3 + 2 * 32]           ; [18]
+    pmulhrsw            m4, m5
+    pmaddubsw           m1, m7, [r3 + 2 * 32]
+    pmulhrsw            m1, m5
+    packuswb            m4, m1
+    movu                [r0 + r1], m4
+
+    pmaddubsw           m4, m6, [r3 - 3 * 32]           ; [13]
+    pmulhrsw            m4, m5
+    pmaddubsw           m1, m7, [r3 - 3 * 32]
+    pmulhrsw            m1, m5
+    packuswb            m4, m1
+    movu                [r0 + r1*2], m4
+
+    pmaddubsw           m4, m6, [r3 - 8 * 32]           ; [8]
+    pmulhrsw            m4, m5
+    pmaddubsw           m1, m7, [r3 - 8 * 32]
+    pmulhrsw            m1, m5
+    packuswb            m4, m1
+    movu                [r0 + r4], m4
+
+    lea                 r0, [r0 + r1 * 4]
+
+    ; rows 24 to 31
+    pmaddubsw           m4, m6, [r3 - 13 * 32]          ; [3]
+    pmulhrsw            m4, m5
+    pmaddubsw           m1, m7, [r3 - 13 * 32]
+    pmulhrsw            m1, m5
+    packuswb            m4, m1
+    movu                [r0], m4
+
+    palignr             m6, m0, m3, 8
+    palignr             m7, m2, m0, 8
+
+    pmaddubsw           m4, m6, [r3 + 14 * 32]          ; [30]
+    pmulhrsw            m4, m5
+    pmaddubsw           m1, m7, [r3 + 14 * 32]
+    pmulhrsw            m1, m5
+    packuswb            m4, m1
+    movu                [r0 + r1], m4
+
+    pmaddubsw           m4, m6, [r3 + 9 * 32]           ; [25]
+    pmulhrsw            m4, m5
+    pmaddubsw           m1, m7, [r3 + 9 * 32]
+    pmulhrsw            m1, m5
+    packuswb            m4, m1
+    movu                [r0 + r1 * 2], m4
+
+    pmaddubsw           m4, m6, [r3 + 4 * 32]           ; [20]
+    pmulhrsw            m4, m5
+    pmaddubsw           m1, m7, [r3 + 4 * 32]
+    pmulhrsw            m1, m5
+    packuswb            m4, m1
+    movu                [r0 + r4], m4
+
+    lea                 r0, [r0 + r1 * 4]
+
+    pmaddubsw           m4, m6, [r3 - 1 * 32]           ; [15]
+    pmulhrsw            m4, m5
+    pmaddubsw           m1, m7, [r3 - 1 * 32]
+    pmulhrsw            m1, m5
+    packuswb            m4, m1
+    movu                [r0], m4
+
+    pmaddubsw           m4, m6, [r3 - 6 * 32]           ; [10]
+    pmulhrsw            m4, m5
+    pmaddubsw           m1, m7, [r3 - 6 * 32]
+    pmulhrsw            m1, m5
+    packuswb            m4, m1
+    movu                [r0 + r1], m4
+
+    pmaddubsw           m4, m6, [r3 - 11 * 32]          ; [5]
+    pmulhrsw            m4, m5
+    pmaddubsw           m1, m7, [r3 - 11 * 32]
+    pmulhrsw            m1, m5
+    packuswb            m4, m1
+    movu                [r0 + r1*2], m4
+
+    pand                m6, [pw_00ff]
+    pand                m7, [pw_00ff]
+    packuswb            m6, m7
+    movu                [r0 + r4], m6
+    RET
+
 %endif  ; ARCH_X86_64
 ;-----------------------------------------------------------------------------------------
 ; end of intra_pred_ang32 angular modes avx2 asm
@@ -17932,206 +18546,6 @@
 %endmacro
 
 INIT_YMM avx2
-cglobal intra_pred_ang32_24, 3, 5, 12
-    mova              m0, [pw_1024]
-    mova              m1, [intra_pred_shuff_0_8]
-    lea               r3, [3 * r1]
-    lea               r4, [c_ang32_mode_24]
-
-    ;row[0, 1]
-    vbroadcasti128    m11, [r2 + 0]
-    pshufb            m2, m11, m1
-    vbroadcasti128    m3, [r2 + 8]
-    pshufb            m3, m1
-    vbroadcasti128    m4, [r2 + 16]
-    pshufb            m4, m1
-    vbroadcasti128    m5, [r2 + 24]
-    pshufb            m5, m1
-
-    mova              m10, [r4 + 0 * mmsize]
-
-    INTRA_PRED_ANG32_CAL_ROW
-    movu              [r0], m7
-    movu              [r0 + r1], m6
-
-    ;row[2, 3]
-    mova              m10, [r4 + 1 * mmsize]
-
-    INTRA_PRED_ANG32_CAL_ROW
-    movu              [r0 + 2 * r1], m7
-    movu              [r0 + r3], m6
-
-    ;row[4, 5]
-    mova              m10, [r4 + 2 * mmsize]
-    lea               r0, [r0 + 4 * r1]
-
-    INTRA_PRED_ANG32_CAL_ROW
-    movu              [r0], m7
-    movu              [r0 + r1], m6
-
-    ;row[6, 7]
-    pslldq            xm11, 1
-    pinsrb            xm11, [r2 + 70], 0
-    vinserti128       m2, m11, xm11, 1
-    pshufb            m2, m1
-    vbroadcasti128    m3, [r2 + 7]
-    pshufb            m3, m1
-    vbroadcasti128    m4, [r2 + 15]
-    pshufb            m4, m1
-    vbroadcasti128    m5, [r2 + 23]
-    pshufb            m5, m1
-
-    mova              m10, [r4 + 3 * mmsize]
-
-    INTRA_PRED_ANG32_CAL_ROW
-    movu              [r0 + 2 * r1], m7
-    movu              [r0 + r3], m6
-
-    ;row[8, 9]
-    add               r4, 4 * mmsize
-    lea               r0, [r0 + 4 * r1]
-    mova              m10, [r4 + 0 * mmsize]
-
-    INTRA_PRED_ANG32_CAL_ROW
-    movu              [r0], m7
-    movu              [r0 + r1], m6
-
-    ;row[10, 11]
-    mova              m10, [r4 + 1 * mmsize]
-
-    INTRA_PRED_ANG32_CAL_ROW
-    movu              [r0 + 2 * r1], m7
-    movu              [r0 + r3], m6
-
-    ;row[12, 13]
-    pslldq            xm11, 1
-    pinsrb            xm11, [r2 + 77], 0
-    vinserti128       m2, m11, xm11, 1
-    pshufb            m2, m1
-    vbroadcasti128    m3, [r2 + 6]
-    pshufb            m3, m1
-    vbroadcasti128    m4, [r2 + 14]
-    pshufb            m4, m1
-    vbroadcasti128    m5, [r2 + 22]
-    pshufb            m5, m1
-
-    mova              m10, [r4 + 2 * mmsize]
-    lea               r0, [r0 + 4 * r1]
-
-    INTRA_PRED_ANG32_CAL_ROW
-    movu              [r0], m7
-    movu              [r0 + r1], m6
-
-    ;row[14, 15]
-    mova              m10, [r4 + 3 * mmsize]
-
-    INTRA_PRED_ANG32_CAL_ROW
-    movu              [r0 + 2 * r1], m7
-    movu              [r0 + r3], m6
-
-    ;row[16, 17]
-    add               r4, 4 * mmsize
-    lea               r0, [r0 + 4 * r1]
-    mova              m10, [r4 + 0 * mmsize]
-
-    INTRA_PRED_ANG32_CAL_ROW
-    movu              [r0], m7
-    movu              [r0 + r1], m6
-
-    ;row[18]
-    mova              m10, [r4 + 1 * mmsize]
-    vperm2i128        m6, m2, m3, 00100000b
-    pmaddubsw         m6, m10
-    pmulhrsw          m6, m0
-    vperm2i128        m7, m4, m5, 00100000b
-    pmaddubsw         m7, m10
-    pmulhrsw          m7, m0
-    packuswb          m6, m7
-    vpermq            m6, m6, 11011000b
-    movu              [r0 + 2 * r1], m6
-
-    ;row[19, 20]
-    pslldq            xm11, 1
-    pinsrb            xm11, [r2 + 83], 0
-    vinserti128       m2, m11, xm11, 1
-    pshufb            m2, m1
-    vbroadcasti128    m3, [r2 + 5]
-    pshufb            m3, m1
-    vbroadcasti128    m4, [r2 + 13]
-    pshufb            m4, m1
-    vbroadcasti128    m5, [r2 + 21]
-    pshufb            m5, m1
-
-    mova              m10, [r4 + 2 * mmsize]
-
-    INTRA_PRED_ANG32_CAL_ROW
-    movu              [r0 + r3], m7
-    lea               r0, [r0 + 4 * r1]
-    movu              [r0], m6
-
-    ;row[21, 22]
-    mova              m10, [r4 + 3 * mmsize]
-
-    INTRA_PRED_ANG32_CAL_ROW
-    movu              [r0 + r1], m7
-    movu              [r0 + 2 * r1], m6
-
-    ;row[23, 24]
-    add               r4, 4 * mmsize
-    mova              m10, [r4 + 0 * mmsize]
-
-    INTRA_PRED_ANG32_CAL_ROW
-    movu              [r0 + r3], m7
-    lea               r0, [r0 + 4 * r1]
-    movu              [r0], m6
-
-    ;row[25, 26]
-    pslldq            xm11, 1
-    pinsrb            xm11, [r2 + 90], 0
-    vinserti128       m2, m11, xm11, 1
-    pshufb            m2, m1
-    vbroadcasti128    m3, [r2 + 4]
-    pshufb            m3, m1
-    vbroadcasti128    m4, [r2 + 12]
-    pshufb            m4, m1
-    vbroadcasti128    m5, [r2 + 20]
-    pshufb            m5, m1
-
-    mova              m10, [r4 + 1 * mmsize]
-
-    INTRA_PRED_ANG32_CAL_ROW
-    movu              [r0 + r1], m7
-    movu              [r0 + 2 * r1], m6
-
-    ;row[27, 28]
-    mova              m10, [r4 + 2 * mmsize]
-
-    INTRA_PRED_ANG32_CAL_ROW
-    movu              [r0 + r3], m7
-    lea               r0, [r0 + 4 * r1]
-    movu              [r0], m6
-
-    ;row[29, 30]
-    mova              m10, [r4 + 3 * mmsize]
-
-    INTRA_PRED_ANG32_CAL_ROW
-    movu              [r0 + r1], m7
-    movu              [r0 + 2 * r1], m6
-
-    ;[row 31]
-    mova              m10, [r4 + 4 * mmsize]
-    vperm2i128        m6, m2, m3, 00100000b
-    pmaddubsw         m6, m10
-    pmulhrsw          m6, m0
-    vperm2i128        m7, m4, m5, 00100000b
-    pmaddubsw         m7, m10
-    pmulhrsw          m7, m0
-    packuswb          m6, m7
-    vpermq            m6, m6, 11011000b
-    movu              [r0 + r3], m6
-    RET
-
-INIT_YMM avx2
 cglobal intra_pred_ang32_23, 3, 5, 12
     mova              m0, [pw_1024]
     mova              m1, [intra_pred_shuff_0_8]


More information about the x265-devel mailing list