[x265] [PATCH] blockfill_s_32x32 sse2 asm code optimization
praveen at multicorewareinc.com
praveen at multicorewareinc.com
Mon Feb 2 12:57:47 CET 2015
# HG changeset patch
# User Praveen Tiwari
# Date 1422878196 -19800
# Branch stable
# Node ID c0d8c77ef0da266a08d1eba2d80d05d0ad1d28fb
# Parent 8d03acd70332ccf642fc7222bf6f9e7f005983ba
blockfill_s_32x32 sse2 asm code optimization
optimized LEA instruction
diff -r 8d03acd70332 -r c0d8c77ef0da source/common/x86/blockcopy8.asm
--- a/source/common/x86/blockcopy8.asm Mon Feb 02 17:13:34 2015 +0530
+++ b/source/common/x86/blockcopy8.asm Mon Feb 02 17:26:36 2015 +0530
@@ -1855,13 +1855,14 @@
;-----------------------------------------------------------------------------
; void blockfill_s_%1x%2(int16_t* dst, intptr_t dstride, int16_t val)
;-----------------------------------------------------------------------------
-%macro BLOCKFILL_S_W32_H4 2
+%macro BLOCKFILL_S_W32_H8 2
INIT_XMM sse2
cglobal blockfill_s_%1x%2, 3, 5, 1, dst, dstStride, val
-mov r3d, %2/4
+mov r3d, %2/8
add r1, r1
+lea r4, [3 * r1]
movd m0, r2d
pshuflw m0, m0, 0
@@ -1883,12 +1884,31 @@
movu [r0 + 2 * r1 + 32], m0
movu [r0 + 2 * r1 + 48], m0
- lea r4, [r0 + 2 * r1]
-
- movu [r4 + r1], m0
- movu [r4 + r1 + 16], m0
- movu [r4 + r1 + 32], m0
- movu [r4 + r1 + 48], m0
+ movu [r0 + r4], m0
+ movu [r0 + r4 + 16], m0
+ movu [r0 + r4 + 32], m0
+ movu [r0 + r4 + 48], m0
+
+ lea r0, [r0 + 4 * r1]
+ movu [r0], m0
+ movu [r0 + 16], m0
+ movu [r0 + 32], m0
+ movu [r0 + 48], m0
+
+ movu [r0 + r1], m0
+ movu [r0 + r1 + 16], m0
+ movu [r0 + r1 + 32], m0
+ movu [r0 + r1 + 48], m0
+
+ movu [r0 + 2 * r1], m0
+ movu [r0 + 2 * r1 + 16], m0
+ movu [r0 + 2 * r1 + 32], m0
+ movu [r0 + 2 * r1 + 48], m0
+
+ movu [r0 + r4], m0
+ movu [r0 + r4 + 16], m0
+ movu [r0 + r4 + 32], m0
+ movu [r0 + r4 + 48], m0
lea r0, [r0 + 4 * r1]
@@ -1898,7 +1918,7 @@
RET
%endmacro
-BLOCKFILL_S_W32_H4 32, 32
+BLOCKFILL_S_W32_H8 32, 32
INIT_YMM avx2
cglobal blockfill_s_32x32, 3, 4, 1
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