[x265] Fwd: [PATCH Review Only] asm-avx2: intra_pred_ang8_33, improved 265.79c -> 185.43c over sse4 asm code

[Praveen Tiwari]

---------- Forwarded message ----------
From: chen <chenm003 at 163.com>
Date: Wed, Feb 25, 2015 at 7:38 PM
Subject: Re: [x265] [PATCH Review Only] asm-avx2: intra_pred_ang8_33,
improved 265.79c -> 185.43c over sse4 asm code
To: Development for x265 <x265-devel at videolan.org>






At 2015-02-25 16:52:00,praveen at multicorewareinc.com wrote:
># HG changeset patch
># User Praveen Tiwari <praveen at multicorewareinc.com>
># Date 1424854196 -19800
># Node ID 177fe9372668b4824c291e967349664766688179
># Parent  02bac78bde961d60d180e59b5260fad93b98d9b4
>asm-avx2: intra_pred_ang8_33, improved 265.79c -> 185.43c over sse4 asm code
>
>intra_ang_8x8[33]       10.56x   185.43          1957.47
>
>diff -r 02bac78bde96 -r 177fe9372668 source/common/x86/asm-primitives.cpp
>--- a/source/common/x86/asm-primitives.cpp	Wed Feb 25 13:46:58 2015 +0530
>+++ b/source/common/x86/asm-primitives.cpp	Wed Feb 25 14:19:56 2015 +0530
>@@ -1813,6 +1813,7 @@
>
>         // intra_pred functions
>         p.cu[BLOCK_8x8].intra_pred[3] = x265_intra_pred_ang8_3_avx2;
>+        p.cu[BLOCK_8x8].intra_pred[33] = x265_intra_pred_ang8_33_avx2;
>     }
> }
> #endif // if HIGH_BIT_DEPTH
>diff -r 02bac78bde96 -r 177fe9372668 source/common/x86/intrapred.h
>--- a/source/common/x86/intrapred.h	Wed Feb 25 13:46:58 2015 +0530
>+++ b/source/common/x86/intrapred.h	Wed Feb 25 14:19:56 2015 +0530
>@@ -158,6 +158,7 @@
>
> #undef DECL_ANG
> void x265_intra_pred_ang8_3_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
>+void x265_intra_pred_ang8_33_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
> void x265_all_angs_pred_4x4_sse4(pixel *dest, pixel *refPix, pixel *filtPix, int bLuma);
> void x265_all_angs_pred_8x8_sse4(pixel *dest, pixel *refPix, pixel *filtPix, int bLuma);
> void x265_all_angs_pred_16x16_sse4(pixel *dest, pixel *refPix, pixel *filtPix, int bLuma);
>diff -r 02bac78bde96 -r 177fe9372668 source/common/x86/intrapred8.asm
>--- a/source/common/x86/intrapred8.asm	Wed Feb 25 13:46:58 2015 +0530
>+++ b/source/common/x86/intrapred8.asm	Wed Feb 25 14:19:56 2015 +0530
>@@ -32087,3 +32087,39 @@
>     movq              [r0 + 2 * r1], xm2
>     movhps            [r0 + r3], xm2
>     RET
>+
>+INIT_YMM avx2
>+cglobal intra_pred_ang8_33, 3,4,5
>+    movu              m3, [pw_1024]
Why constant are unaligned?

[Praveen] Seems alignment issue here, mova crashing on avx2 machine.

>+    vbroadcasti128    m0, [r2 + 1]
it is Exception Type 6, please check and confirm it compatible with
unaligned address

[Praveen] Sadly most of documents don't talk about alignment regarding
this instruction including Intel® Architecture Instruction Set
Extensions Programming Reference but I verified with encoder seems it
works fine with unaligned address too.
>+
>+    pshufb            m1, m0, [c_ang8_src1_9_2_10]
>+    pshufb            m2, m0, [c_ang8_src3_11_4_12]
>+    pshufb            m4, m0, [c_ang8_src5_13_5_13]
>+    pshufb            m4, m0, [c_ang8_src5_13_5_13]
Why duplicated?

[Praveen] Yeah, duplicate code here, has been fixed locally.


>+    pshufb            m0,     [c_ang8_src6_14_7_15]
>+
>+    pmaddubsw         m1, [c_ang8_26_20]
>+    pmulhrsw          m1, m3
>+    pmaddubsw         m2, [c_ang8_14_8]
>+    pmulhrsw          m2, m3
>+    pmaddubsw         m4, [c_ang8_2_28]
>+    pmulhrsw          m4, m3
>+    pmaddubsw         m0, [c_ang8_22_16]
>+    pmulhrsw          m0, m3
>+    packuswb          m1, m2
>+    packuswb          m4, m0
>+
>+    lea               r3, [3 * r1]
>+    movq              [r0], xm1
>+    vextracti128      xm2, m1, 1
>+    movq              [r0 + r1], xm2
>+    movhps            [r0 + 2 * r1], xm1
>+    movhps            [r0 + r3], xm2
>+    lea               r0, [r0 + 4 * r1]
>+    movq              [r0], xm4
>+    vextracti128      xm2, m4, 1
>+    movq              [r0 + r1], xm2
>+    movhps            [r0 + 2 * r1], xm4
>+    movhps            [r0 +
r3], xm2
>+    RET
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