[x265] [PATCH] all_angs_pred_8x8: optimize mov instruction

praveen at multicorewareinc.com praveen at multicorewareinc.com
Wed Jan 14 11:28:40 CET 2015


# HG changeset patch
# User Praveen Tiwari
# Date 1421231301 -19800
# Node ID 2d617be47353f481c6c6e7e235cee1ba58f340f7
# Parent  7ad510c96fea192a9e834a8340905b54bc49aa9d
all_angs_pred_8x8: optimize mov instruction

diff -r 7ad510c96fea -r 2d617be47353 source/common/x86/intrapred8.asm
--- a/source/common/x86/intrapred8.asm	Wed Jan 14 12:06:54 2015 +0530
+++ b/source/common/x86/intrapred8.asm	Wed Jan 14 15:58:21 2015 +0530
@@ -10659,35 +10659,35 @@
     ; mode 18 [row 0, 1, 2, 3, 4, 5, 6, 7]
 
     movh          m1,          [r2]
-    movh          [r0 + 1024], m1
 
     pslldq        m2,          m1,         1
     pinsrb        m2,          [r2 + 1 + 16],   0
-    movh          [r0 + 1032], m2
+    punpcklqdq    m1,          m2
+    movu          [r0 + 1024], m1
 
     pslldq        m2,          1
     pinsrb        m2,          [r2 + 2 + 16],   0
-    movh          [r0 + 1040], m2
-
-    pslldq        m2,          1
-    pinsrb        m2,          [r2 + 3 + 16],   0
-    movh          [r0 + 1048], m2
-
-    pslldq        m2,          1
-    pinsrb        m2,          [r2 + 4 + 16],   0
-    movh          [r0 + 1056], m2
-
-    pslldq        m2,          1
+
+    pslldq        m0,          m2,          1
+    pinsrb        m0,          [r2 + 3 + 16],   0
+    punpcklqdq    m2,          m0
+    movu          [r0 + 1040], m2
+
+    pslldq        m0,          1
+    pinsrb        m0,          [r2 + 4 + 16],   0
+
+    pslldq        m2,          m0,              1
     pinsrb        m2,          [r2 + 5 + 16],   0
-    movh          [r0 + 1064], m2
+    punpcklqdq    m0,          m2
+    movu          [r0 + 1056], m0
 
     pslldq        m2,          1
     pinsrb        m2,          [r2 + 6 + 16],   0
-    movh          [r0 + 1072], m2
-
-    pslldq        m2,          1
-    pinsrb        m2,          [r2 + 7 + 16],   0
-    movh          [r0 + 1080], m2
+
+    pslldq        m0,           m2,             1
+    pinsrb        m0,          [r2 + 7 + 16],   0
+    punpcklqdq    m2,          m0
+    movu          [r0 + 1072], m2
 
     ; mode 19 [row 0, 1]
 


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