[x265] [PATCH] asm: avx2 code for intra_pred_ang32x32 mode 4 & 32, improved 8709c->4618c, 47%
dnyaneshwar at multicorewareinc.com
dnyaneshwar at multicorewareinc.com
Tue Jun 9 13:43:35 CEST 2015
# HG changeset patch
# User Dnyaneshwar G <dnyaneshwar at multicorewareinc.com>
# Date 1433849586 -19800
# Tue Jun 09 17:03:06 2015 +0530
# Node ID 7cfd60ed1696d523444aa3cfbf9827c34471b25e
# Parent 05df60c805d3f423db573885eb9f27b17dbc12a7
asm: avx2 code for intra_pred_ang32x32 mode 4 & 32, improved 8709c->4618c, 47%
diff -r 05df60c805d3 -r 7cfd60ed1696 source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Tue Jun 09 12:31:29 2015 +0530
+++ b/source/common/x86/asm-primitives.cpp Tue Jun 09 17:03:06 2015 +0530
@@ -1258,6 +1258,8 @@
p.cu[BLOCK_32x32].intra_pred[2] = x265_intra_pred_ang32_2_avx2;
p.cu[BLOCK_32x32].intra_pred[3] = x265_intra_pred_ang32_3_avx2;
+ p.cu[BLOCK_32x32].intra_pred[4] = x265_intra_pred_ang32_4_avx2;
+ p.cu[BLOCK_32x32].intra_pred[32] = x265_intra_pred_ang32_32_avx2;
p.cu[BLOCK_32x32].intra_pred[33] = x265_intra_pred_ang32_33_avx2;
p.cu[BLOCK_32x32].intra_pred[34] = x265_intra_pred_ang32_2_avx2;
diff -r 05df60c805d3 -r 7cfd60ed1696 source/common/x86/intrapred.h
--- a/source/common/x86/intrapred.h Tue Jun 09 12:31:29 2015 +0530
+++ b/source/common/x86/intrapred.h Tue Jun 09 17:03:06 2015 +0530
@@ -277,6 +277,7 @@
void x265_intra_pred_ang32_34_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
void x265_intra_pred_ang32_2_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
void x265_intra_pred_ang32_3_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
+void x265_intra_pred_ang32_4_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
void x265_intra_pred_ang32_26_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
void x265_intra_pred_ang32_27_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
void x265_intra_pred_ang32_28_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
diff -r 05df60c805d3 -r 7cfd60ed1696 source/common/x86/intrapred16.asm
--- a/source/common/x86/intrapred16.asm Tue Jun 09 12:31:29 2015 +0530
+++ b/source/common/x86/intrapred16.asm Tue Jun 09 17:03:06 2015 +0530
@@ -13344,6 +13344,223 @@
call ang16_mode_3_33
RET
+
+;; angle 32, modes 4 and 32
+cglobal ang32_mode_4_32
+ test r6d, r6d
+
+ movu m0, [r2 + 2] ; [16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
+ movu m1, [r2 + 4] ; [17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2]
+
+ punpcklwd m3, m0, m1 ; [13 12 12 11 11 10 10 9 5 4 4 3 3 2 2 1]
+ punpckhwd m0, m1 ; [17 16 16 15 15 14 14 13 9 8 8 7 7 6 6 5]
+
+ movu m1, [r2 + 18] ; [24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9]
+ movu m4, [r2 + 20] ; [25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10]
+ punpcklwd m2, m1, m4 ; [21 20 20 19 19 18 18 17 13 12 12 11 11 10 10 9]
+ punpckhwd m1, m4 ; [25 24 24 23 23 22 22 21 17 16 16 15 15 14 14 13]
+
+ pmaddwd m4, m3, [r3 - 13 * 32] ; [5]
+ paddd m4, [pd_16]
+ psrld m4, 5
+ pmaddwd m5, m0, [r3 - 13 * 32]
+ paddd m5, [pd_16]
+ psrld m5, 5
+ packusdw m4, m5
+
+ pmaddwd m5, m3, [r3 + 8 * 32] ; [26]
+ paddd m5, [pd_16]
+ psrld m5, 5
+ pmaddwd m8, m0, [r3 + 8 * 32]
+ paddd m8, [pd_16]
+ psrld m8, 5
+ packusdw m5, m8
+
+ palignr m6, m0, m3, 4 ; [14 13 13 12 12 11 11 10 6 5 5 4 4 3 3 2]
+ pmaddwd m6, [r3 - 3 * 32] ; [15]
+ paddd m6, [pd_16]
+ psrld m6, 5
+ palignr m7, m2, m0, 4 ; [18 17 17 16 16 15 15 14 10 9 9 8 8 7 7 6]
+ pmaddwd m7, [r3 - 3 * 32]
+ paddd m7, [pd_16]
+ psrld m7, 5
+ packusdw m6, m7
+
+ palignr m8, m0, m3, 8 ; [15 14 14 13 13 12 12 11 7 6 6 5 5 4 4 3]
+ pmaddwd m7, m8, [r3 - 14 * 32] ; [4]
+ paddd m7, [pd_16]
+ psrld m7, 5
+ palignr m9, m2, m0, 8 ; [19 18 18 17 17 16 16 15 11 10 10 9 9 8 8 7]
+ pmaddwd m10, m9, [r3 - 14 * 32]
+ paddd m10, [pd_16]
+ psrld m10, 5
+ packusdw m7, m10
+
+ pmaddwd m8, [r3 + 7 * 32] ; [25]
+ paddd m8, [pd_16]
+ psrld m8, 5
+ pmaddwd m9, [r3 + 7 * 32]
+ paddd m9, [pd_16]
+ psrld m9, 5
+ packusdw m8, m9
+
+ palignr m9, m0, m3, 12
+ pmaddwd m9, [r3 - 4 * 32] ; [14]
+ paddd m9, [pd_16]
+ psrld m9, 5
+ palignr m3, m2, m0, 12
+ pmaddwd m3, [r3 - 4 * 32]
+ paddd m3, [pd_16]
+ psrld m3, 5
+ packusdw m9, m3
+
+ pmaddwd m10, m0, [r3 - 15 * 32] ; [3]
+ paddd m10, [pd_16]
+ psrld m10, 5
+ pmaddwd m3, m2, [r3 - 15 * 32]
+ paddd m3, [pd_16]
+ psrld m3, 5
+ packusdw m10, m3
+
+ pmaddwd m11, m0, [r3 + 6 * 32] ; [24]
+ paddd m11, [pd_16]
+ psrld m11, 5
+ pmaddwd m3, m2, [r3 + 6 * 32]
+ paddd m3, [pd_16]
+ psrld m3, 5
+ packusdw m11, m3
+
+ TRANSPOSE_STORE_AVX2 4, 5, 6, 7, 8, 9, 10, 11, 12, 3, 0
+
+ palignr m4, m2, m0, 4
+ pmaddwd m4, [r3 - 5* 32] ; [13]
+ paddd m4, [pd_16]
+ psrld m4, 5
+ palignr m5, m1, m2, 4
+ pmaddwd m5, [r3 - 5 * 32]
+ paddd m5, [pd_16]
+ psrld m5, 5
+ packusdw m4, m5
+
+ palignr m6, m2, m0, 8
+ pmaddwd m5, m6, [r3 - 16 * 32] ; [2]
+ paddd m5, [pd_16]
+ psrld m5, 5
+ palignr m7, m1, m2, 8
+ pmaddwd m8, m7, [r3 - 16 * 32]
+ paddd m8, [pd_16]
+ psrld m8, 5
+ packusdw m5, m8
+
+ pmaddwd m6, [r3 + 5 * 32] ; [23]
+ paddd m6, [pd_16]
+ psrld m6, 5
+ pmaddwd m7, [r3 + 5 * 32]
+ paddd m7, [pd_16]
+ psrld m7, 5
+ packusdw m6, m7
+
+ palignr m7, m2, m0, 12
+ pmaddwd m7, [r3 - 6 * 32] ; [12]
+ paddd m7, [pd_16]
+ psrld m7, 5
+ palignr m8, m1, m2, 12
+ pmaddwd m8, [r3 - 6 * 32]
+ paddd m8, [pd_16]
+ psrld m8, 5
+ packusdw m7, m8
+
+ movu m0, [r2 + 34] ; [32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17]
+ pmaddwd m8, m2, [r3 - 17 * 32] ; [1]
+ paddd m8, [pd_16]
+ psrld m8, 5
+ pmaddwd m9, m1, [r3 - 17 * 32]
+ paddd m9, [pd_16]
+ psrld m9, 5
+ packusdw m8, m9
+
+ palignr m3, m0, m0, 2 ; [ x 32 31 30 29 28 27 26 x 24 23 22 21 20 19 18]
+ punpcklwd m0, m3 ; [29 29 28 28 27 27 26 22 21 20 20 19 19 18 18 17]
+
+ pmaddwd m9, m2, [r3 + 4 * 32] ; [22]
+ paddd m9, [pd_16]
+ psrld m9, 5
+ pmaddwd m3, m1, [r3 + 4 * 32]
+ paddd m3, [pd_16]
+ psrld m3, 5
+ packusdw m9, m3
+
+ palignr m10, m1, m2, 4
+ pmaddwd m10, [r3 - 7 * 32] ; [11]
+ paddd m10, [pd_16]
+ psrld m10, 5
+ palignr m11, m0, m1, 4
+ pmaddwd m11, [r3 - 7 * 32]
+ paddd m11, [pd_16]
+ psrld m11, 5
+ packusdw m10, m11
+
+ palignr m3, m1, m2, 8
+ pmaddwd m3, [r3 - 18 * 32] ; [0]
+ paddd m3, [pd_16]
+ psrld m3, 5
+ palignr m0, m1, 8
+ pmaddwd m0, [r3 - 18 * 32]
+ paddd m0, [pd_16]
+ psrld m0, 5
+ packusdw m3, m0
+ TRANSPOSE_STORE_AVX2 4, 5, 6, 7, 8, 9, 10, 3, 0, 1, 16
+ ret
+
+cglobal intra_pred_ang32_4, 3,8,13
+ add r2, 128
+ xor r6d, r6d
+ lea r3, [ang_table_avx2 + 18 * 32]
+ add r1d, r1d
+ lea r4, [r1 * 3]
+ lea r7, [r0 + 8 * r1]
+
+ call ang16_mode_4_32
+
+ add r2, 22
+ lea r0, [r0 + 32]
+
+ call ang32_mode_4_32
+
+ add r2, 10
+ lea r0, [r7 + 8 * r1]
+
+ call ang16_mode_4_32
+
+ add r2, 22
+ lea r0, [r0 + 32]
+
+ call ang32_mode_4_32
+ RET
+
+cglobal intra_pred_ang32_32, 3,7,13
+ xor r6d, r6d
+ inc r6d
+ lea r3, [ang_table_avx2 + 18 * 32]
+ add r1d, r1d
+ lea r4, [r1 * 3]
+ lea r5, [r0 + 32]
+
+ call ang16_mode_4_32
+
+ add r2, 22
+
+ call ang32_mode_4_32
+
+ add r2, 10
+ mov r0, r5
+
+ call ang16_mode_4_32
+
+ add r2, 22
+
+ call ang32_mode_4_32
+ RET
;-------------------------------------------------------------------------------------------------------
; end of avx2 code for intra_pred_ang32 mode 2 to 34
;-------------------------------------------------------------------------------------------------------
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