[x265] [PATCH] asm: 10bpp avx2 code for intra_pred_ang32x32 mode 8 & 28
dnyaneshwar at multicorewareinc.com
dnyaneshwar at multicorewareinc.com
Wed Jun 10 13:04:14 CEST 2015
# HG changeset patch
# User Dnyaneshwar G <dnyaneshwar at multicorewareinc.com>
# Date 1433933746 -19800
# Wed Jun 10 16:25:46 2015 +0530
# Node ID 6fad2ccf68ce2419290b238fd57c49f64fc62d3e
# Parent 8e973542ac0e8c458c18a979a48f3b6cc6b3896a
asm: 10bpp avx2 code for intra_pred_ang32x32 mode 8 & 28
performance improvement over SSE:
intra_ang_32x32[ 8] 7837c->4431c, 43%
intra_ang_32x32[28] 5660c->2916c, 48%
diff -r 8e973542ac0e -r 6fad2ccf68ce source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Wed Jun 10 15:28:59 2015 +0530
+++ b/source/common/x86/asm-primitives.cpp Wed Jun 10 16:25:46 2015 +0530
@@ -1262,6 +1262,8 @@
p.cu[BLOCK_32x32].intra_pred[5] = x265_intra_pred_ang32_5_avx2;
p.cu[BLOCK_32x32].intra_pred[6] = x265_intra_pred_ang32_6_avx2;
p.cu[BLOCK_32x32].intra_pred[7] = x265_intra_pred_ang32_7_avx2;
+ p.cu[BLOCK_32x32].intra_pred[8] = x265_intra_pred_ang32_8_avx2;
+ p.cu[BLOCK_32x32].intra_pred[28] = x265_intra_pred_ang32_28_avx2;
p.cu[BLOCK_32x32].intra_pred[29] = x265_intra_pred_ang32_29_avx2;
p.cu[BLOCK_32x32].intra_pred[30] = x265_intra_pred_ang32_30_avx2;
p.cu[BLOCK_32x32].intra_pred[31] = x265_intra_pred_ang32_31_avx2;
diff -r 8e973542ac0e -r 6fad2ccf68ce source/common/x86/intrapred.h
--- a/source/common/x86/intrapred.h Wed Jun 10 15:28:59 2015 +0530
+++ b/source/common/x86/intrapred.h Wed Jun 10 16:25:46 2015 +0530
@@ -281,6 +281,7 @@
void x265_intra_pred_ang32_5_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
void x265_intra_pred_ang32_6_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
void x265_intra_pred_ang32_7_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
+void x265_intra_pred_ang32_8_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
void x265_intra_pred_ang32_26_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
void x265_intra_pred_ang32_27_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
void x265_intra_pred_ang32_28_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
diff -r 8e973542ac0e -r 6fad2ccf68ce source/common/x86/intrapred16.asm
--- a/source/common/x86/intrapred16.asm Wed Jun 10 15:28:59 2015 +0530
+++ b/source/common/x86/intrapred16.asm Wed Jun 10 16:25:46 2015 +0530
@@ -14186,6 +14186,210 @@
call ang32_mode_7_29
RET
+
+;; angle 32, modes 8 and 28
+cglobal ang32_mode_8_28
+ test r6d, r6d
+
+ movu m0, [r2 + 2] ; [16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
+ movu m1, [r2 + 4] ; [17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2]
+
+ punpcklwd m3, m0, m1 ; [13 12 12 11 11 10 10 9 5 4 4 3 3 2 2 1]
+ punpckhwd m0, m1 ; [17 16 16 15 15 14 14 13 9 8 8 7 7 6 6 5]
+
+ movu m2, [r2 + 18] ; [24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9]
+ movu m4, [r2 + 20] ; [25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10]
+ punpcklwd m2, m4 ; [21 20 20 19 19 18 18 17 13 12 12 11 11 10 10 9]
+
+ pmaddwd m4, m3, [r3 + 6 * 32] ; [21]
+ paddd m4, [pd_16]
+ psrld m4, 5
+ pmaddwd m5, m0, [r3 + 6 * 32]
+ paddd m5, [pd_16]
+ psrld m5, 5
+ packusdw m4, m5
+
+ pmaddwd m5, m3, [r3 + 11 * 32] ; [26]
+ paddd m5, [pd_16]
+ psrld m5, 5
+ pmaddwd m8, m0, [r3 + 11 * 32]
+ paddd m8, [pd_16]
+ psrld m8, 5
+ packusdw m5, m8
+
+ pmaddwd m6, m3, [r3 + 16 * 32] ; [31]
+ paddd m6, [pd_16]
+ psrld m6, 5
+ pmaddwd m9, m0, [r3 + 16 * 32]
+ paddd m9, [pd_16]
+ psrld m9, 5
+ packusdw m6, m9
+
+ palignr m11, m0, m3, 4
+ pmaddwd m7, m11, [r3 - 11 * 32] ; [4]
+ paddd m7, [pd_16]
+ psrld m7, 5
+ palignr m1, m2, m0, 4
+ pmaddwd m8, m1, [r3 - 11 * 32]
+ paddd m8, [pd_16]
+ psrld m8, 5
+ packusdw m7, m8
+
+ pmaddwd m8, m11, [r3 - 6 * 32] ; [9]
+ paddd m8, [pd_16]
+ psrld m8, 5
+ pmaddwd m9, m1, [r3 - 6 * 32]
+ paddd m9, [pd_16]
+ psrld m9, 5
+ packusdw m8, m9
+
+ pmaddwd m9, m11, [r3 - 1 * 32] ; [14]
+ paddd m9, [pd_16]
+ psrld m9, 5
+ pmaddwd m10, m1, [r3 - 1 * 32]
+ paddd m10, [pd_16]
+ psrld m10, 5
+ packusdw m9, m10
+
+ pmaddwd m10, m11, [r3 + 4 * 32] ; [19]
+ paddd m10, [pd_16]
+ psrld m10, 5
+ pmaddwd m12, m1, [r3 + 4 * 32]
+ paddd m12, [pd_16]
+ psrld m12, 5
+ packusdw m10, m12
+
+ pmaddwd m11, [r3 + 9 * 32] ; [24]
+ paddd m11, [pd_16]
+ psrld m11, 5
+ pmaddwd m1, [r3 + 9 * 32]
+ paddd m1, [pd_16]
+ psrld m1, 5
+ packusdw m11, m1
+
+ TRANSPOSE_STORE_AVX2 4, 5, 6, 7, 8, 9, 10, 11, 12, 1, 0
+
+ palignr m4, m0, m3, 4
+ pmaddwd m4, [r3 + 14 * 32] ; [29]
+ paddd m4, [pd_16]
+ psrld m4, 5
+ palignr m5, m2, m0, 4
+ pmaddwd m5, [r3 + 14 * 32]
+ paddd m5, [pd_16]
+ psrld m5, 5
+ packusdw m4, m5
+
+ palignr m1, m0, m3, 8
+ pmaddwd m5, m1, [r3 - 13 * 32] ; [2]
+ paddd m5, [pd_16]
+ psrld m5, 5
+ palignr m10, m2, m0, 8
+ pmaddwd m6, m10, [r3 - 13 * 32]
+ paddd m6, [pd_16]
+ psrld m6, 5
+ packusdw m5, m6
+
+ pmaddwd m6, m1, [r3 - 8 * 32] ; [7]
+ paddd m6, [pd_16]
+ psrld m6, 5
+ pmaddwd m8, m10, [r3 - 8 * 32]
+ paddd m8, [pd_16]
+ psrld m8, 5
+ packusdw m6, m8
+
+ pmaddwd m7, m1, [r3 - 3 * 32] ; [12]
+ paddd m7, [pd_16]
+ psrld m7, 5
+ pmaddwd m8, m10, [r3 - 3 * 32]
+ paddd m8, [pd_16]
+ psrld m8, 5
+ packusdw m7, m8
+
+ pmaddwd m8, m1, [r3 + 2 * 32] ; [17]
+ paddd m8, [pd_16]
+ psrld m8, 5
+ pmaddwd m9, m10, [r3 + 2 * 32]
+ paddd m9, [pd_16]
+ psrld m9, 5
+ packusdw m8, m9
+
+ pmaddwd m9, m1, [r3 + 7 * 32] ; [22]
+ paddd m9, [pd_16]
+ psrld m9, 5
+ pmaddwd m11, m10, [r3 + 7 * 32]
+ paddd m11, [pd_16]
+ psrld m11, 5
+ packusdw m9, m11
+
+ pmaddwd m1, [r3 + 12 * 32] ; [27]
+ paddd m1, [pd_16]
+ psrld m1, 5
+ pmaddwd m10, [r3 + 12 * 32]
+ paddd m10, [pd_16]
+ psrld m10, 5
+ packusdw m1, m10
+
+ palignr m11, m0, m3, 12
+ pmaddwd m11, [r3 - 15 * 32] ; [0]
+ paddd m11, [pd_16]
+ psrld m11, 5
+ palignr m2, m0, 12
+ pmaddwd m2, [r3 - 15 * 32]
+ paddd m2, [pd_16]
+ psrld m2, 5
+ packusdw m11, m2
+ TRANSPOSE_STORE_AVX2 4, 5, 6, 7, 8, 9, 1, 11, 0, 2, 16
+ ret
+
+cglobal intra_pred_ang32_8, 3,8,13
+ add r2, 128
+ xor r6d, r6d
+ lea r3, [ang_table_avx2 + 15 * 32]
+ add r1d, r1d
+ lea r4, [r1 * 3]
+ lea r7, [r0 + 8 * r1]
+
+ call ang16_mode_8_28
+
+ add r2, 4
+ lea r0, [r0 + 32]
+
+ call ang32_mode_8_28
+
+ add r2, 28
+ lea r0, [r7 + 8 * r1]
+
+ call ang16_mode_8_28
+
+ add r2, 4
+ lea r0, [r0 + 32]
+
+ call ang32_mode_8_28
+ RET
+
+cglobal intra_pred_ang32_28, 3,7,13
+ xor r6d, r6d
+ inc r6d
+ lea r3, [ang_table_avx2 + 15 * 32]
+ add r1d, r1d
+ lea r4, [r1 * 3]
+ lea r5, [r0 + 32]
+
+ call ang16_mode_8_28
+
+ add r2, 4
+
+ call ang32_mode_8_28
+
+ add r2, 28
+ mov r0, r5
+
+ call ang16_mode_8_28
+
+ add r2, 4
+
+ call ang32_mode_8_28
+ RET
;-------------------------------------------------------------------------------------------------------
; end of avx2 code for intra_pred_ang32 mode 2 to 34
;-------------------------------------------------------------------------------------------------------
More information about the x265-devel
mailing list