[x265] [PATCH] asm: interp_4tap_vert_X[6xN] avx2 10bit code for i420, i422
rajesh at multicorewareinc.com
rajesh at multicorewareinc.com
Thu Jun 11 11:13:31 CEST 2015
# HG changeset patch
# User Rajesh Paulraj<rajesh at multicorewareinc.com>
# Date 1434001187 -19800
# Thu Jun 11 11:09:47 2015 +0530
# Node ID 07e20891148d8c645ab8955d0537ed145b8e0976
# Parent 6245476add8f0562e3ccb657f572ff94fe96adf0
asm: interp_4tap_vert_X[6xN] avx2 10bit code for i420,i422
avx2:
chroma_vpp[ 6x8][i420] 6.70x 1086.77 7279.75
chroma_vps[ 6x8][i420] 5.71x 1048.69 5988.26
chroma_vsp[ 6x8][i420] 5.84x 1148.31 6706.06
chroma_vss[ 6x8][i420] 4.89x 1049.28 5130.71
chroma_vpp[ 6x16][i422] 7.09x 2011.41 14253.51
chroma_vps[ 6x16][i422] 6.24x 1865.18 11634.61
chroma_vsp[ 6x16][i422] 7.02x 2010.37 14117.57
chroma_vss[ 6x16][i422] 5.64x 1865.62 10513.17
sse4:
chroma_vpp[ 6x8][i420] 5.32x 1321.86 7026.91
chroma_vps[ 6x8][i420] 4.72x 1247.41 5893.77
chroma_vsp[ 6x8][i420] 5.21x 1322.85 6889.80
chroma_vss[ 6x8][i420] 4.49x 1155.30 5193.04
chroma_vpp[ 6x16][i422] 5.97x 2375.30 14184.56
chroma_vps[ 6x16][i422] 4.90x 2149.63 10538.98
chroma_vsp[ 6x16][i422] 6.08x 2334.50 14182.23
chroma_vss[ 6x16][i422] 5.02x 1988.08 9972.00
diff -r 6245476add8f -r 07e20891148d source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Wed Jun 10 11:54:27 2015 +0530
+++ b/source/common/x86/asm-primitives.cpp Thu Jun 11 11:09:47 2015 +0530
@@ -1733,6 +1733,10 @@
p.chroma[X265_CSP_I422].pu[CHROMA_422_8x64].filter_vss = x265_interp_4tap_vert_ss_8x64_avx2;
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_6x8].filter_vss = x265_interp_4tap_vert_ss_6x8_avx2;
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_6x8].filter_vsp = x265_interp_4tap_vert_sp_6x8_avx2;
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_6x8].filter_vps = x265_interp_4tap_vert_ps_6x8_avx2;
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_6x8].filter_vpp = x265_interp_4tap_vert_pp_6x8_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_12x16].filter_vpp = x265_interp_4tap_vert_pp_12x16_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_12x16].filter_vps = x265_interp_4tap_vert_ps_12x16_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_12x16].filter_vss = x265_interp_4tap_vert_ss_12x16_avx2;
@@ -1777,6 +1781,10 @@
p.chroma[X265_CSP_I420].pu[CHROMA_420_32x16].filter_vsp = x265_interp_4tap_vert_sp_32x16_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_32x24].filter_vsp = x265_interp_4tap_vert_sp_32x24_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_32x32].filter_vsp = x265_interp_4tap_vert_sp_32x32_avx2;
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_6x16].filter_vss = x265_interp_4tap_vert_ss_6x16_avx2;
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_6x16].filter_vsp = x265_interp_4tap_vert_sp_6x16_avx2;
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_6x16].filter_vps = x265_interp_4tap_vert_ps_6x16_avx2;
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_6x16].filter_vpp = x265_interp_4tap_vert_pp_6x16_avx2;
p.chroma[X265_CSP_I422].pu[CHROMA_422_12x32].filter_vpp = x265_interp_4tap_vert_pp_12x32_avx2;
p.chroma[X265_CSP_I422].pu[CHROMA_422_12x32].filter_vps = x265_interp_4tap_vert_ps_12x32_avx2;
p.chroma[X265_CSP_I422].pu[CHROMA_422_12x32].filter_vss = x265_interp_4tap_vert_ss_12x32_avx2;
diff -r 6245476add8f -r 07e20891148d source/common/x86/ipfilter16.asm
--- a/source/common/x86/ipfilter16.asm Wed Jun 10 11:54:27 2015 +0530
+++ b/source/common/x86/ipfilter16.asm Thu Jun 11 11:09:47 2015 +0530
@@ -4820,6 +4820,152 @@
;-----------------------------------------------------------------------------------------------------------------
; void interp_4tap_vert(int16_t *src, intptr_t srcStride, int16_t *dst, intptr_t dstStride, int coeffIdx)
;-----------------------------------------------------------------------------------------------------------------
+%macro FILTER_VER_CHROMA_AVX2_6xN 2
+INIT_YMM avx2
+%if ARCH_X86_64
+cglobal interp_4tap_vert_%2_6x%1, 4, 7, 10
+ mov r4d, r4m
+ add r1d, r1d
+ add r3d, r3d
+ shl r4d, 6
+
+%ifdef PIC
+ lea r5, [tab_ChromaCoeffV]
+ add r5, r4
+%else
+ lea r5, [tab_ChromaCoeffV + r4]
+%endif
+
+ sub r0, r1
+ mov r6d, %1/4
+
+%ifidn %2,pp
+ vbroadcasti128 m8, [pd_32]
+%elifidn %2, sp
+ mova m8, [pd_524800]
+%else
+ vbroadcasti128 m8, [tab_c_n32768]
+%endif
+
+.loopH:
+ movu xm0, [r0]
+ movu xm1, [r0 + r1]
+ punpckhwd xm2, xm0, xm1
+ punpcklwd xm0, xm1
+ vinserti128 m0, m0, xm2, 1
+ pmaddwd m0, [r5]
+
+ movu xm2, [r0 + r1 * 2]
+ punpckhwd xm3, xm1, xm2
+ punpcklwd xm1, xm2
+ vinserti128 m1, m1, xm3, 1
+ pmaddwd m1, [r5]
+
+ lea r4, [r1 * 3]
+ movu xm3, [r0 + r4]
+ punpckhwd xm4, xm2, xm3
+ punpcklwd xm2, xm3
+ vinserti128 m2, m2, xm4, 1
+ pmaddwd m4, m2, [r5 + 1 * mmsize]
+ pmaddwd m2, [r5]
+ paddd m0, m4
+
+ lea r0, [r0 + r1 * 4]
+ movu xm4, [r0]
+ punpckhwd xm5, xm3, xm4
+ punpcklwd xm3, xm4
+ vinserti128 m3, m3, xm5, 1
+ pmaddwd m5, m3, [r5 + 1 * mmsize]
+ pmaddwd m3, [r5]
+ paddd m1, m5
+
+ movu xm5, [r0 + r1]
+ punpckhwd xm6, xm4, xm5
+ punpcklwd xm4, xm5
+ vinserti128 m4, m4, xm6, 1
+ pmaddwd m6, m4, [r5 + 1 * mmsize]
+ pmaddwd m4, [r5]
+ paddd m2, m6
+
+ movu xm6, [r0 + r1 * 2]
+ punpckhwd xm7, xm5, xm6
+ punpcklwd xm5, xm6
+ vinserti128 m5, m5, xm7, 1
+ pmaddwd m7, m5, [r5 + 1 * mmsize]
+ pmaddwd m5, [r5]
+ paddd m3, m7
+ lea r4, [r3 * 3]
+%ifidn %2,ss
+ psrad m0, 6
+ psrad m1, 6
+ psrad m2, 6
+ psrad m3, 6
+%else
+ paddd m0, m8
+ paddd m1, m8
+ paddd m2, m8
+ paddd m3, m8
+%ifidn %2,pp
+ psrad m0, 6
+ psrad m1, 6
+ psrad m2, 6
+ psrad m3, 6
+%elifidn %2, sp
+ psrad m0, 10
+ psrad m1, 10
+ psrad m2, 10
+ psrad m3, 10
+%else
+ psrad m0, 2
+ psrad m1, 2
+ psrad m2, 2
+ psrad m3, 2
+%endif
+%endif
+
+ packssdw m0, m1
+ packssdw m2, m3
+ vpermq m0, m0, q3120
+ vpermq m2, m2, q3120
+ pxor m5, m5
+ mova m9, [pw_pixel_max]
+%ifidn %2,pp
+ CLIPW m0, m5, m9
+ CLIPW m2, m5, m9
+%elifidn %2, sp
+ CLIPW m0, m5, m9
+ CLIPW m2, m5, m9
+%endif
+
+ vextracti128 xm1, m0, 1
+ vextracti128 xm3, m2, 1
+ movq [r2], xm0
+ pextrd [r2 + 8], xm0, 2
+ movq [r2 + r3], xm1
+ pextrd [r2 + r3 + 8], xm1, 2
+ movq [r2 + r3 * 2], xm2
+ pextrd [r2 + r3 * 2 + 8], xm2, 2
+ movq [r2 + r4], xm3
+ pextrd [r2 + r4 + 8], xm3, 2
+
+ lea r2, [r2 + r3 * 4]
+ dec r6d
+ jnz .loopH
+ RET
+%endif
+%endmacro
+FILTER_VER_CHROMA_AVX2_6xN 8, pp
+FILTER_VER_CHROMA_AVX2_6xN 8, ps
+FILTER_VER_CHROMA_AVX2_6xN 8, ss
+FILTER_VER_CHROMA_AVX2_6xN 8, sp
+FILTER_VER_CHROMA_AVX2_6xN 16, pp
+FILTER_VER_CHROMA_AVX2_6xN 16, ps
+FILTER_VER_CHROMA_AVX2_6xN 16, ss
+FILTER_VER_CHROMA_AVX2_6xN 16, sp
+
+;-----------------------------------------------------------------------------------------------------------------
+; void interp_4tap_vert(int16_t *src, intptr_t srcStride, int16_t *dst, intptr_t dstStride, int coeffIdx)
+;-----------------------------------------------------------------------------------------------------------------
%macro FILTER_VER_CHROMA_W16_16xN_avx2 3
INIT_YMM avx2
cglobal interp_4tap_vert_%2_16x%1, 5, 6, %3
diff -r 6245476add8f -r 07e20891148d source/common/x86/ipfilter8.h
--- a/source/common/x86/ipfilter8.h Wed Jun 10 11:54:27 2015 +0530
+++ b/source/common/x86/ipfilter8.h Thu Jun 11 11:09:47 2015 +0530
@@ -145,7 +145,8 @@
SETUP_CHROMA_420_VERT_FUNC_DEF(32, 24, cpu); \
SETUP_CHROMA_420_VERT_FUNC_DEF(24, 32, cpu); \
SETUP_CHROMA_420_VERT_FUNC_DEF(32, 8, cpu); \
- SETUP_CHROMA_420_VERT_FUNC_DEF(8, 32, cpu)
+ SETUP_CHROMA_420_VERT_FUNC_DEF(8, 32, cpu); \
+ SETUP_CHROMA_420_VERT_FUNC_DEF(6, 8, cpu);
#define CHROMA_420_VERT_FILTERS_SSE4(cpu) \
SETUP_CHROMA_420_VERT_FUNC_DEF(2, 4, cpu); \
@@ -173,7 +174,8 @@
SETUP_CHROMA_420_VERT_FUNC_DEF(32, 48, cpu); \
SETUP_CHROMA_420_VERT_FUNC_DEF(24, 64, cpu); \
SETUP_CHROMA_420_VERT_FUNC_DEF(32, 16, cpu); \
- SETUP_CHROMA_420_VERT_FUNC_DEF(8, 64, cpu);
+ SETUP_CHROMA_420_VERT_FUNC_DEF(8, 64, cpu); \
+ SETUP_CHROMA_420_VERT_FUNC_DEF(6, 16, cpu);
#define CHROMA_422_VERT_FILTERS_SSE4(cpu) \
SETUP_CHROMA_420_VERT_FUNC_DEF(2, 8, cpu); \
More information about the x265-devel
mailing list